/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn0_phydfe_ctrl.h
//[Revision time]   : Wed Dec 26 19:16:55 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN0_PHYDFE_CTRL_REGS_H__
#define __BN0_PHYDFE_CTRL_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN0_PHYDFE_CTRL CR Definitions                     
//
//****************************************************************************

#define BN0_PHYDFE_CTRL_BASE                                   0x83080000

#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE000) // E000
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR               (BN0_PHYDFE_CTRL_BASE + 0XE200) // E200
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_ADDR              (BN0_PHYDFE_CTRL_BASE + 0XE204) // E204
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_1_ADDR              (BN0_PHYDFE_CTRL_BASE + 0XE208) // E208
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_2_ADDR              (BN0_PHYDFE_CTRL_BASE + 0XE210) // E210
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_3_ADDR              (BN0_PHYDFE_CTRL_BASE + 0XE214) // E214
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_4_ADDR              (BN0_PHYDFE_CTRL_BASE + 0XE218) // E218
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE400) // E400
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE404) // E404
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE408) // E408
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE40C) // E40C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE410) // E410
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE414) // E414
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE418) // E418
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_ADDR                (BN0_PHYDFE_CTRL_BASE + 0XE41C) // E41C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE440) // E440
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE444) // E444
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE448) // E448
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE44C) // E44C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE450) // E450
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE454) // E454
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE458) // E458
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE45C) // E45C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE460) // E460
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE464) // E464
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE468) // E468
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0XE46C) // E46C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE470) // E470
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE474) // E474
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_ADDR       (BN0_PHYDFE_CTRL_BASE + 0XE478) // E478
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE47C) // E47C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE480) // E480
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE484) // E484
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE488) // E488
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE48C) // E48C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE490) // E490
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE494) // E494
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE498) // E498
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE49C) // E49C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4A0) // E4A0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4A4) // E4A4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4A8) // E4A8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4AC) // E4AC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4B0) // E4B0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4B4) // E4B4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4B8) // E4B8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4BC) // E4BC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4C0) // E4C0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4C4) // E4C4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4C8) // E4C8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4CC) // E4CC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4D0) // E4D0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4D4) // E4D4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4D8) // E4D8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4DC) // E4DC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE4E0) // E4E0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4E4) // E4E4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4E8) // E4E8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4EC) // E4EC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4F0) // E4F0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4F4) // E4F4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4F8) // E4F8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE4FC) // E4FC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE500) // E500
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE504) // E504
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE508) // E508
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE50c) // E50C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_ADDR      (BN0_PHYDFE_CTRL_BASE + 0XE510) // E510
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE514) // E514
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE518) // E518
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE51C) // E51C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE520) // E520
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE524) // E524
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_ADDR     (BN0_PHYDFE_CTRL_BASE + 0XE528) // E528
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE52C) // E52C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE530) // E530
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE534) // E534
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE538) // E538
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE53C) // E53C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE540) // E540
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE544) // E544
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE548) // E548
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE54C) // E54C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE550) // E550
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE554) // E554
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE558) // E558
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE55C) // E55C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE560) // E560
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE564) // E564
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE568) // E568
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE56C) // E56C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE570) // E570
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE574) // E574
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE578) // E578
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE57C) // E57C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE580) // E580
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE584) // E584
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE588) // E588
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE58C) // E58C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE590) // E590
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE594) // E594
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE598) // E598
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE59C) // E59C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5A0) // E5A0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5A4) // E5A4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5A8) // E5A8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5AC) // E5AC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5B0) // E5B0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5B4) // E5B4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5B8) // E5B8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5BC) // E5BC
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5C0) // E5C0
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5C4) // E5C4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE5C8) // E5C8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE700) // E700
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE704) // E704
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE708) // E708
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE70C) // E70C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE710) // E710
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE714) // E714
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE718) // E718
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE71C) // E71C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE720) // E720
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE724) // E724
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE728) // E728
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE72C) // E72C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE730) // E730
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_ADDR (BN0_PHYDFE_CTRL_BASE + 0XE734) // E734
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE738) // E738
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE73C) // E73C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE740) // E740
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE744) // E744
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE748) // E748
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_ADDR            (BN0_PHYDFE_CTRL_BASE + 0XE74C) // E74C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR            (BN0_PHYDFE_CTRL_BASE + 0XE750) // E750
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE754) // E754
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR             (BN0_PHYDFE_CTRL_BASE + 0XE758) // E758
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_ADDR            (BN0_PHYDFE_CTRL_BASE + 0XE75C) // E75C
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_00_ADDR               (BN0_PHYDFE_CTRL_BASE + 0XE798) // E798
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_01_ADDR               (BN0_PHYDFE_CTRL_BASE + 0XE79C) // E79C
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_00_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7A0) // E7A0
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_01_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7A4) // E7A4
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_02_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7A8) // E7A8
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_03_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7AC) // E7AC
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_04_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7B0) // E7B0
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_05_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7B4) // E7B4
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_06_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7B8) // E7B8
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_07_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7BC) // E7BC
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_08_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7C0) // E7C0
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_09_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7C4) // E7C4
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_10_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7C8) // E7C8
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_11_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7CC) // E7CC
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_12_ADDR          (BN0_PHYDFE_CTRL_BASE + 0XE7D0) // E7D0
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_ADDR             (BN0_PHYDFE_CTRL_BASE + 0xF000) // F000
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_ADDR        (BN0_PHYDFE_CTRL_BASE + 0xF004) // F004
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR        (BN0_PHYDFE_CTRL_BASE + 0xF008) // F008
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_02_B0_ADDR        (BN0_PHYDFE_CTRL_BASE + 0xF00C) // F00C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR       (BN0_PHYDFE_CTRL_BASE + 0xF010) // F010
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF014) // F014
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF018) // F018
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF01C) // F01C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF020) // F020
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF024) // F024
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF028) // F028
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF02C) // F02C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF030) // F030
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF034) // F034
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF038) // F038
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF03C) // F03C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF040) // F040
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF044) // F044
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF048) // F048
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF04C) // F04C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF050) // F050
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF054) // F054
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF058) // F058
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF05C) // F05C
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xF060) // F060
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR                (BN0_PHYDFE_CTRL_BASE + 0xF064) // F064
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR                (BN0_PHYDFE_CTRL_BASE + 0xF068) // F068
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR                (BN0_PHYDFE_CTRL_BASE + 0xF06C) // F06C
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR     (BN0_PHYDFE_CTRL_BASE + 0xF070) // F070
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF074) // F074
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF078) // F078
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF07C) // F07C
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR            (BN0_PHYDFE_CTRL_BASE + 0xF080) // F080
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF084) // F084
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF090) // F090
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF094) // F094
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF098) // F098
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF09C) // F09C
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_4_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF0A0) // F0A0
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_ADDR              (BN0_PHYDFE_CTRL_BASE + 0xF0A4) // F0A4
#define BN0_PHYDFE_CTRL_RO_BAND_WB_RSSI_AMP_AVG_ADDR           (BN0_PHYDFE_CTRL_BASE + 0xF0B0) // F0B0
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_CTL_00_RD_ADDR        (BN0_PHYDFE_CTRL_BASE + 0xF0B4) // F0B4
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_AFIFO_RD_ADDR         (BN0_PHYDFE_CTRL_BASE + 0xF0B8) // F0B8
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX0_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0BC) // F0BC
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX1_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0C0) // F0C0
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_00_RD_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0C4) // F0C4
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_01_RD_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0C8) // F0C8
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_02_RD_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0CC) // F0CC
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_03_RD_ADDR      (BN0_PHYDFE_CTRL_BASE + 0xF0D0) // F0D0
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF100) // F100
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF104) // F104
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF108) // F108
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_ADDR          (BN0_PHYDFE_CTRL_BASE + 0xF10C) // F10C
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_00_ADDR     (BN0_PHYDFE_CTRL_BASE + 0xF120) // F120
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_01_ADDR     (BN0_PHYDFE_CTRL_BASE + 0xF124) // F124
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_02_ADDR     (BN0_PHYDFE_CTRL_BASE + 0xF128) // F128
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFC00) // FC00
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFC04) // FC04
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFC08) // FC08
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFC0C) // FC0C
#define BN0_PHYDFE_CTRL_CR_BAND_RFINTF_CTRL_0_ADDR             (BN0_PHYDFE_CTRL_BASE + 0xFC20) // FC20
#define BN0_PHYDFE_CTRL_RO_BAND_RFINTF_FLAG_00_ADDR            (BN0_PHYDFE_CTRL_BASE + 0xFDE0) // FDE0
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_0_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFDE4) // FDE4
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_1_ADDR               (BN0_PHYDFE_CTRL_BASE + 0xFDE8) // FDE8




/* =====================================================================================

  ---CR_BAND_WF2GPSEXTBT_CTRL (0x83080000 + 0XE000)---

    CR_BAND_WPHY2COEX_WF_CH[3..0] - (RW) [DE] BBP control CR
    RESERVED4[10..4]             - (RO) Reserved bits
    CR_BAND_WF2BT_RX_MANUAL_ACTIVE[11] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_RX_MANUAL_MODE[12] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_RXON_GBAND[13] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_RXON_ABAND[14] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_RXON[15]       - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TX_MANUAL_BW[16] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TX_MANUAL_ACTIVE[17] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TX_MANUAL_MODE[18] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TXON_GBAND[19] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TXON_ABAND[20] - (RW) [DE] BBP control CR
    CR_BAND_WF2BT_TXON[21]       - (RW) [DE] BBP control CR
    CR_BAND_WF2EXT_TX_MANUAL_ACTIVE[22] - (RW) [DE] BBP control CR
    CR_BAND_WF2EXT_TX_MANUAL_MODE[23] - (RW) [DE] BBP control CR
    CR_BAND_WF2EXT_TXON_GBAND[24] - (RW) [DE] BBP control CR
    CR_BAND_WF2EXT_TXON_ABAND[25] - (RW) [DE] BBP control CR
    CR_BAND_WF2EXT_TXON[26]      - (RW) [DE] BBP control CR
    CR_BAND_WF2GPS_TX_MANUAL_ACTIVE[27] - (RW) [DE] BBP control CR
    CR_BAND_WF2GPS_TX_MANUAL_MODE[28] - (RW) [DE] BBP control CR
    CR_BAND_WF2GPS_TXON_GBAND[29] - (RW) [DE] BBP control CR
    CR_BAND_WF2GPS_TXON_ABAND[30] - (RW) [DE] BBP control CR
    CR_BAND_WF2GPS_TXON[31]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_MASK 0x80000000                // CR_BAND_WF2GPS_TXON[31]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_ABAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_ABAND_MASK 0x40000000                // CR_BAND_WF2GPS_TXON_ABAND[30]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_ABAND_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_GBAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_GBAND_MASK 0x20000000                // CR_BAND_WF2GPS_TXON_GBAND[29]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TXON_GBAND_SHFT 29
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_MODE_MASK 0x10000000                // CR_BAND_WF2GPS_TX_MANUAL_MODE[28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_MODE_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_ACTIVE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_ACTIVE_MASK 0x08000000                // CR_BAND_WF2GPS_TX_MANUAL_ACTIVE[27]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2GPS_TX_MANUAL_ACTIVE_SHFT 27
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_MASK 0x04000000                // CR_BAND_WF2EXT_TXON[26]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_ABAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_ABAND_MASK 0x02000000                // CR_BAND_WF2EXT_TXON_ABAND[25]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_ABAND_SHFT 25
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_GBAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_GBAND_MASK 0x01000000                // CR_BAND_WF2EXT_TXON_GBAND[24]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TXON_GBAND_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_MODE_MASK 0x00800000                // CR_BAND_WF2EXT_TX_MANUAL_MODE[23]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_MODE_SHFT 23
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_ACTIVE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_ACTIVE_MASK 0x00400000                // CR_BAND_WF2EXT_TX_MANUAL_ACTIVE[22]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2EXT_TX_MANUAL_ACTIVE_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_MASK 0x00200000                // CR_BAND_WF2BT_TXON[21]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_SHFT 21
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_ABAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_ABAND_MASK 0x00100000                // CR_BAND_WF2BT_TXON_ABAND[20]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_ABAND_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_GBAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_GBAND_MASK 0x00080000                // CR_BAND_WF2BT_TXON_GBAND[19]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TXON_GBAND_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_MODE_MASK 0x00040000                // CR_BAND_WF2BT_TX_MANUAL_MODE[18]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_MODE_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_ACTIVE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_ACTIVE_MASK 0x00020000                // CR_BAND_WF2BT_TX_MANUAL_ACTIVE[17]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_ACTIVE_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_BW_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_BW_MASK 0x00010000                // CR_BAND_WF2BT_TX_MANUAL_BW[16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_TX_MANUAL_BW_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_MASK 0x00008000                // CR_BAND_WF2BT_RXON[15]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_SHFT 15
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_ABAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_ABAND_MASK 0x00004000                // CR_BAND_WF2BT_RXON_ABAND[14]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_ABAND_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_GBAND_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_GBAND_MASK 0x00002000                // CR_BAND_WF2BT_RXON_GBAND[13]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RXON_GBAND_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_MODE_MASK 0x00001000                // CR_BAND_WF2BT_RX_MANUAL_MODE[12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_MODE_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_ACTIVE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_ACTIVE_MASK 0x00000800                // CR_BAND_WF2BT_RX_MANUAL_ACTIVE[11]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WF2BT_RX_MANUAL_ACTIVE_SHFT 11
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WPHY2COEX_WF_CH_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WPHY2COEX_WF_CH_MASK 0x0000000F                // CR_BAND_WPHY2COEX_WF_CH[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF2GPSEXTBT_CTRL_CR_BAND_WPHY2COEX_WF_CH_SHFT 0

/* =====================================================================================

  ---CR_BAND_CCK_CSD_SEL (0x83080000 + 0XE200)---

    CR_BAND_TX_CCK_CSD_SEL_1[4..0] - (RW) [CSD] CCK TX1 CSD DELAY
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_BAND_TX_CCK_CSD_SEL_2[12..8] - (RW) [CSD] CCK TX2 CSD DELAY
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_BAND_TX_CCK_CSD_SEL_3[20..16] - (RW) [CSD] CCK TX3 CSD DELAY
    RESERVED21[27..21]           - (RO) Reserved bits
    CR_BAND_TX_CCK_CSD_SEL_MANUAL[29..28] - (RW) [DE] enable cck csd sel manual
    RESERVED30[30]               - (RO) Reserved bits
    CR_BAND_TX_CCK_CSD_SEL_MANUAL_EN[31] - (RW) [DE] enable cck csd sel manual mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_EN_MASK 0x80000000                // CR_BAND_TX_CCK_CSD_SEL_MANUAL_EN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_EN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_MASK 0x30000000                // CR_BAND_TX_CCK_CSD_SEL_MANUAL[29..28]
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_MANUAL_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_3_MASK 0x001F0000                // CR_BAND_TX_CCK_CSD_SEL_3[20..16]
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_3_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_2_MASK 0x00001F00                // CR_BAND_TX_CCK_CSD_SEL_2[12..8]
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_2_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_1_MASK 0x0000001F                // CR_BAND_TX_CCK_CSD_SEL_1[4..0]
#define BN0_PHYDFE_CTRL_CR_BAND_CCK_CSD_SEL_CR_BAND_TX_CCK_CSD_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND_TX_PRECOMP_0 (0x83080000 + 0XE204)---

    RESERVED0[21..0]             - (RO) Reserved bits
    CR_BAND_TX_PRECOMP_CFOE_ALPHA_TF[26..22] - (RW) band0 tx precomp long-term avg. CFOE TF alpha coef., 0, 0.5 , 1
    CR_BAND_TX_PRECOMP_CFOE_ALPHA_NORMAL[31..27] - (RW) band0 tx precomp long-term avg. CFOE normal alpha coef., 0, 0.5 , 1

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_NORMAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_NORMAL_MASK 0xF8000000                // CR_BAND_TX_PRECOMP_CFOE_ALPHA_NORMAL[31..27]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_NORMAL_SHFT 27
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_TF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_TF_MASK 0x07C00000                // CR_BAND_TX_PRECOMP_CFOE_ALPHA_TF[26..22]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_0_CR_BAND_TX_PRECOMP_CFOE_ALPHA_TF_SHFT 22

/* =====================================================================================

  ---CR_BAND_TX_PRECOMP_1 (0x83080000 + 0XE208)---

    CR_BAND_TX_PRECOMP_CFOE_SW_AVG_0[19..0] - (RW) band0 tx precomp long-term avg. CFOE by SW
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_1_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_0_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_1_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_0_MASK 0x000FFFFF                // CR_BAND_TX_PRECOMP_CFOE_SW_AVG_0[19..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_1_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_0_SHFT 0

/* =====================================================================================

  ---CR_BAND_TX_PRECOMP_2 (0x83080000 + 0XE210)---

    CR_BAND_TX_PRECOMP_CFOE_SW_AVG_1[19..0] - (RW) band0 tx precomp long-term avg. CFOE by SW
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_2_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_2_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_1_MASK 0x000FFFFF                // CR_BAND_TX_PRECOMP_CFOE_SW_AVG_1[19..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_2_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_1_SHFT 0

/* =====================================================================================

  ---CR_BAND_TX_PRECOMP_3 (0x83080000 + 0XE214)---

    CR_BAND_TX_PRECOMP_CFOE_SW_AVG_2[19..0] - (RW) band0 tx precomp long-term avg. CFOE by SW
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_3_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_3_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_2_MASK 0x000FFFFF                // CR_BAND_TX_PRECOMP_CFOE_SW_AVG_2[19..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_3_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_2_SHFT 0

/* =====================================================================================

  ---CR_BAND_TX_PRECOMP_4 (0x83080000 + 0XE218)---

    CR_BAND_TX_PRECOMP_CFOE_SW_AVG_3[19..0] - (RW) band0 tx precomp long-term avg. CFOE by SW
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_4_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_4_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_4_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_3_MASK 0x000FFFFF                // CR_BAND_TX_PRECOMP_CFOE_SW_AVG_3[19..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TX_PRECOMP_4_CR_BAND_TX_PRECOMP_CFOE_SW_AVG_3_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_00 (0x83080000 + 0XE400)---

    CR_BAND_TPC_TOTAL_PWR_NON_HETB[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_TOTAL_PWR_NON_HETB_MAN[8] - (RW) [DE] BBP control CR
    RESERVED9[15..9]             - (RO) Reserved bits
    CR_BAND_TPC_TOTAL_PWR_HETB[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_TOTAL_PWR_HETB_MAN[24] - (RW) [DE] BBP control CR
    RESERVED25[29..25]           - (RO) Reserved bits
    CR_BAND_TPC_PWR_LATCH[30]    - (RW) [DE] BBP control CR
    CR_BAND_TPC_PWR_LATCH_MAN[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_MAN_MASK 0x80000000                // CR_BAND_TPC_PWR_LATCH_MAN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_MAN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_MASK 0x40000000                // CR_BAND_TPC_PWR_LATCH[30]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_PWR_LATCH_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_MAN_MASK 0x01000000                // CR_BAND_TPC_TOTAL_PWR_HETB_MAN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_MAN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_MASK 0x00FF0000                // CR_BAND_TPC_TOTAL_PWR_HETB[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_HETB_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_MAN_MASK 0x00000100                // CR_BAND_TPC_TOTAL_PWR_NON_HETB_MAN[8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_MAN_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_MASK 0x000000FF                // CR_BAND_TPC_TOTAL_PWR_NON_HETB[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_00_CR_BAND_TPC_TOTAL_PWR_NON_HETB_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_01 (0x83080000 + 0XE404)---

    CR_BAND_TPC_FCC_PWR_SKU2[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_FCC_PWR_SKU2_MAN[8] - (RW) [DE] BBP control CR
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_BAND_TPC_TOTAL_TXPWR_IND[12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_TOTAL_TXPWR_IND_MAN[13] - (RW) [DE] BBP control CR
    RESERVED14[15..14]           - (RO) Reserved bits
    CR_BAND_TPC_MU_BACKOFF_BYPASS[16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_PHY2MAC_FORCE_EN[17] - (RW) [DE] BBP control CR
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_PHY2MAC_FORCE_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_PHY2MAC_FORCE_EN_MASK 0x00020000                // CR_BAND_TPC_PHY2MAC_FORCE_EN[17]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_PHY2MAC_FORCE_EN_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_MU_BACKOFF_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_MU_BACKOFF_BYPASS_MASK 0x00010000                // CR_BAND_TPC_MU_BACKOFF_BYPASS[16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_MU_BACKOFF_BYPASS_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_MAN_MASK 0x00002000                // CR_BAND_TPC_TOTAL_TXPWR_IND_MAN[13]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_MAN_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_MASK 0x00001000                // CR_BAND_TPC_TOTAL_TXPWR_IND[12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_TOTAL_TXPWR_IND_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_MAN_MASK 0x00000100                // CR_BAND_TPC_FCC_PWR_SKU2_MAN[8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_MAN_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_MASK 0x000000FF                // CR_BAND_TPC_FCC_PWR_SKU2[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_01_CR_BAND_TPC_FCC_PWR_SKU2_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_02 (0x83080000 + 0XE408)---

    CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MAN[8] - (RW) [DE] BBP control CR
    RESERVED9[15..9]             - (RO) Reserved bits
    CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR[21..16] - (RW) [DE] BBP control CR
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MAN[24] - (RW) [DE] BBP control CR
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MAN_MASK 0x01000000                // CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MAN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MAN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_MASK 0x003F0000                // CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR[21..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_FACTOR_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MAN_MASK 0x00000100                // CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MAN[8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MAN_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_MASK 0x000000FF                // CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_02_CR_BAND_TPC_HE_MU_SCALE_DW_RU_IDX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_03 (0x83080000 + 0XE40C)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_PHY2MAC_UPH[20..16] - (RW) [DE] BBP control CR
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_BAND_TPC_PHY2MAC_UPH_MAN[24] - (RW) [DE] BBP control CR
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_MAN_MASK 0x01000000                // CR_BAND_TPC_PHY2MAC_UPH_MAN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_MAN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_MASK 0x001F0000                // CR_BAND_TPC_PHY2MAC_UPH[20..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_03_CR_BAND_TPC_PHY2MAC_UPH_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_CTL_04 (0x83080000 + 0XE410)---

    CR_BAND_TPC_TX_PWR_DBM[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_TX_PWR_DBM_MAN[8] - (RW) [DE] BBP control CR
    RESERVED9[15..9]             - (RO) Reserved bits
    CR_BAND_TPC_PHY2MAC_TXPWR[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_PHY2MAC_TXPWR_MAN[24] - (RW) [DE] BBP control CR
    RESERVED25[29..25]           - (RO) Reserved bits
    CR_BAND_TPC_PHY2MAC_MINTXPWR[30] - (RW) [DE] BBP control CR
    CR_BAND_TPC_PHY2MAC_MINTXPWR_MAN[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_MAN_MASK 0x80000000                // CR_BAND_TPC_PHY2MAC_MINTXPWR_MAN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_MAN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_MASK 0x40000000                // CR_BAND_TPC_PHY2MAC_MINTXPWR[30]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_MINTXPWR_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_MAN_MASK 0x01000000                // CR_BAND_TPC_PHY2MAC_TXPWR_MAN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_MAN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_MASK 0x00FF0000                // CR_BAND_TPC_PHY2MAC_TXPWR[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_PHY2MAC_TXPWR_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_MAN_MASK 0x00000100                // CR_BAND_TPC_TX_PWR_DBM_MAN[8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_MAN_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_MASK 0x000000FF                // CR_BAND_TPC_TX_PWR_DBM[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_04_CR_BAND_TPC_TX_PWR_DBM_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_05 (0x83080000 + 0XE414)---

    CR_BAND_TPC_STA_MAX_MCS0_PWR[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_TX_PWR_DBM_VLD_CNT[12..8] - (RW) [DE] BBP control CR
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_BAND_TPC_SKU2_MIN_RU_PREAMBLE_BYPASS[16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_LCR_PWR_BOOST_EN[17] - (RW) [DE] BBP control CR
    CR_BAND_TPC_8080_USE_DBW160_TYPE[18] - (RW) [DE] BBP control CR
    RESERVED19[27..19]           - (RO) Reserved bits
    CR_BAND_TPC_PWR_SYNC_RST_BYPASS[28] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HEMU_FCC_MIN_CMP_BYPASS[29] - (RW) [DE] BBP control CR
    CR_BAND_TPC_PWR_LATCH_METHOD[31..30] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_LATCH_METHOD_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_LATCH_METHOD_MASK 0xC0000000                // CR_BAND_TPC_PWR_LATCH_METHOD[31..30]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_LATCH_METHOD_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_HEMU_FCC_MIN_CMP_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_HEMU_FCC_MIN_CMP_BYPASS_MASK 0x20000000                // CR_BAND_TPC_HEMU_FCC_MIN_CMP_BYPASS[29]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_HEMU_FCC_MIN_CMP_BYPASS_SHFT 29
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_SYNC_RST_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_SYNC_RST_BYPASS_MASK 0x10000000                // CR_BAND_TPC_PWR_SYNC_RST_BYPASS[28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_PWR_SYNC_RST_BYPASS_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_8080_USE_DBW160_TYPE_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_8080_USE_DBW160_TYPE_MASK 0x00040000                // CR_BAND_TPC_8080_USE_DBW160_TYPE[18]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_8080_USE_DBW160_TYPE_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_LCR_PWR_BOOST_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_LCR_PWR_BOOST_EN_MASK 0x00020000                // CR_BAND_TPC_SKU2_LCR_PWR_BOOST_EN[17]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_LCR_PWR_BOOST_EN_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_MIN_RU_PREAMBLE_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_MIN_RU_PREAMBLE_BYPASS_MASK 0x00010000                // CR_BAND_TPC_SKU2_MIN_RU_PREAMBLE_BYPASS[16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_SKU2_MIN_RU_PREAMBLE_BYPASS_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_TX_PWR_DBM_VLD_CNT_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_TX_PWR_DBM_VLD_CNT_MASK 0x00001F00                // CR_BAND_TPC_TX_PWR_DBM_VLD_CNT[12..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_TX_PWR_DBM_VLD_CNT_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_STA_MAX_MCS0_PWR_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_STA_MAX_MCS0_PWR_MASK 0x000000FF                // CR_BAND_TPC_STA_MAX_MCS0_PWR[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_05_CR_BAND_TPC_STA_MAX_MCS0_PWR_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_06 (0x83080000 + 0XE418)---

    CR_BAND_TPC_NON_HETB_TXPWR_1TX_BACK_OFF[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_NON_HETB_TXPWR_2TX_BACK_OFF[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_NON_HETB_TXPWR_3TX_BACK_OFF[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_NON_HETB_TXPWR_4TX_BACK_OFF[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HETB_TXPWR_1TX_BACK_OFF[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HETB_TXPWR_2TX_BACK_OFF[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HETB_TXPWR_3TX_BACK_OFF[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_HETB_TXPWR_4TX_BACK_OFF[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_4TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_4TX_BACK_OFF_MASK 0xF0000000                // CR_BAND_TPC_HETB_TXPWR_4TX_BACK_OFF[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_4TX_BACK_OFF_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_3TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_3TX_BACK_OFF_MASK 0x0F000000                // CR_BAND_TPC_HETB_TXPWR_3TX_BACK_OFF[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_3TX_BACK_OFF_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_2TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_2TX_BACK_OFF_MASK 0x00F00000                // CR_BAND_TPC_HETB_TXPWR_2TX_BACK_OFF[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_2TX_BACK_OFF_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_1TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_1TX_BACK_OFF_MASK 0x000F0000                // CR_BAND_TPC_HETB_TXPWR_1TX_BACK_OFF[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_HETB_TXPWR_1TX_BACK_OFF_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_4TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_4TX_BACK_OFF_MASK 0x0000F000                // CR_BAND_TPC_NON_HETB_TXPWR_4TX_BACK_OFF[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_4TX_BACK_OFF_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_3TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_3TX_BACK_OFF_MASK 0x00000F00                // CR_BAND_TPC_NON_HETB_TXPWR_3TX_BACK_OFF[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_3TX_BACK_OFF_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_2TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_2TX_BACK_OFF_MASK 0x000000F0                // CR_BAND_TPC_NON_HETB_TXPWR_2TX_BACK_OFF[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_2TX_BACK_OFF_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_1TX_BACK_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_1TX_BACK_OFF_MASK 0x0000000F                // CR_BAND_TPC_NON_HETB_TXPWR_1TX_BACK_OFF[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_06_CR_BAND_TPC_NON_HETB_TXPWR_1TX_BACK_OFF_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_CTL_07 (0x83080000 + 0XE41C)---

    CR_BAND_TPC_HETB_1TX_OFFSET[5..0] - (RW) [DE] BBP control CR
    RESERVED6[7..6]              - (RO) Reserved bits
    CR_BAND_TPC_HETB_2TX_OFFSET[13..8] - (RW) [DE] BBP control CR
    RESERVED14[15..14]           - (RO) Reserved bits
    CR_BAND_TPC_HETB_3TX_OFFSET[21..16] - (RW) [DE] BBP control CR
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_BAND_TPC_HETB_4TX_OFFSET[29..24] - (RW) [DE] BBP control CR
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_4TX_OFFSET_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_4TX_OFFSET_MASK 0x3F000000                // CR_BAND_TPC_HETB_4TX_OFFSET[29..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_4TX_OFFSET_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_3TX_OFFSET_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_3TX_OFFSET_MASK 0x003F0000                // CR_BAND_TPC_HETB_3TX_OFFSET[21..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_3TX_OFFSET_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_2TX_OFFSET_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_2TX_OFFSET_MASK 0x00003F00                // CR_BAND_TPC_HETB_2TX_OFFSET[13..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_2TX_OFFSET_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_1TX_OFFSET_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_1TX_OFFSET_MASK 0x0000003F                // CR_BAND_TPC_HETB_1TX_OFFSET[5..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_CTL_07_CR_BAND_TPC_HETB_1TX_OFFSET_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW20_00 (0x83080000 + 0XE440)---

    CR_BAND_TPC_BMFGN_BW20_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW20_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW20_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_BW20_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_BW20_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_BW20_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_BW20_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_BW20_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_BW20_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_00_CR_BAND_TPC_BMFGN_BW20_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW20_01 (0x83080000 + 0XE444)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_BW20_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW20_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW20_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW20_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW20_01_CR_BAND_TPC_BMFGN_BW20_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW40_00 (0x83080000 + 0XE448)---

    CR_BAND_TPC_BMFGN_BW40_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW40_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW40_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_BW40_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_BW40_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_BW40_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_BW40_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_BW40_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_BW40_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_00_CR_BAND_TPC_BMFGN_BW40_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW40_01 (0x83080000 + 0XE44C)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_BW40_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW40_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW40_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW40_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW40_01_CR_BAND_TPC_BMFGN_BW40_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW80_00 (0x83080000 + 0XE450)---

    CR_BAND_TPC_BMFGN_BW80_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW80_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW80_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_BW80_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_BW80_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_BW80_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_BW80_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_BW80_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_BW80_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_00_CR_BAND_TPC_BMFGN_BW80_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW80_01 (0x83080000 + 0XE454)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_BW80_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW80_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW80_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW80_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW80_01_CR_BAND_TPC_BMFGN_BW80_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW160_00 (0x83080000 + 0XE458)---

    CR_BAND_TPC_BMFGN_BW160_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW160_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW160_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_BW160_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_BW160_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_BW160_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_BW160_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_BW160_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_BW160_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_00_CR_BAND_TPC_BMFGN_BW160_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_BW160_01 (0x83080000 + 0XE45C)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_BW160_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_BW160_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_BW160_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_BW160_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_BW160_01_CR_BAND_TPC_BMFGN_BW160_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU26_00 (0x83080000 + 0XE460)---

    CR_BAND_TPC_BMFGN_RU26_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU26_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU26_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_RU26_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_RU26_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_RU26_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_RU26_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_RU26_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_RU26_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_00_CR_BAND_TPC_BMFGN_RU26_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU26_01 (0x83080000 + 0XE464)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_RU26_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU26_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU26_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU26_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU26_01_CR_BAND_TPC_BMFGN_RU26_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU52_00 (0x83080000 + 0XE468)---

    CR_BAND_TPC_BMFGN_RU52_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU52_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU52_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_RU52_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_RU52_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_RU52_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_RU52_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_RU52_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_RU52_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_00_CR_BAND_TPC_BMFGN_RU52_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU52_01 (0x83080000 + 0XE46C)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_RU52_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU52_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU52_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU52_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU52_01_CR_BAND_TPC_BMFGN_RU52_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU106_00 (0x83080000 + 0XE470)---

    CR_BAND_TPC_BMFGN_RU106_3STS_3TX[3..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_2STS_4TX[7..4] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_2STS_3TX[11..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_2STS_2TX[15..12] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_1STS_4TX[19..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_1STS_3TX[23..20] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_1STS_2TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_1STS_1TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_1TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU106_1STS_1TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_1TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_2TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU106_1STS_2TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_3TX_MASK 0x00F00000                // CR_BAND_TPC_BMFGN_RU106_1STS_3TX[23..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_3TX_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_4TX_MASK 0x000F0000                // CR_BAND_TPC_BMFGN_RU106_1STS_4TX[19..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_1STS_4TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_2TX_MASK 0x0000F000                // CR_BAND_TPC_BMFGN_RU106_2STS_2TX[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_2TX_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_3TX_MASK 0x00000F00                // CR_BAND_TPC_BMFGN_RU106_2STS_3TX[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_4TX_MASK 0x000000F0                // CR_BAND_TPC_BMFGN_RU106_2STS_4TX[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_2STS_4TX_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_3STS_3TX_MASK 0x0000000F                // CR_BAND_TPC_BMFGN_RU106_3STS_3TX[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_00_CR_BAND_TPC_BMFGN_RU106_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_BFG_RU106_01 (0x83080000 + 0XE474)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_BAND_TPC_BMFGN_RU106_4STS_4TX[27..24] - (RW) [DE] BBP control CR
    CR_BAND_TPC_BMFGN_RU106_3STS_4TX[31..28] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_3STS_4TX_MASK 0xF0000000                // CR_BAND_TPC_BMFGN_RU106_3STS_4TX[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_3STS_4TX_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_4STS_4TX_MASK 0x0F000000                // CR_BAND_TPC_BMFGN_RU106_4STS_4TX[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_BFG_RU106_01_CR_BAND_TPC_BMFGN_RU106_4STS_4TX_SHFT 24

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_CCK_00 (0x83080000 + 0XE478)---

    CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_CCK_00_CR_BAND_TPC_SKU2_FCC_BF_X_CCK20_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_LG20_00 (0x83080000 + 0XE47C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_00_CR_BAND_TPC_SKU2_FCC_BF_X_LG20_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_LG20_01 (0x83080000 + 0XE480)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_LG20_01_CR_BAND_TPC_SKU2_FCC_BF_O_LG20_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_00 (0x83080000 + 0XE484)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_01 (0x83080000 + 0XE488)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_02 (0x83080000 + 0XE48C)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW20_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW20_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_03 (0x83080000 + 0XE490)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_04 (0x83080000 + 0XE494)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW20_05 (0x83080000 + 0XE498)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW20_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW20_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW20_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_00 (0x83080000 + 0XE49C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_01 (0x83080000 + 0XE4A0)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_02 (0x83080000 + 0XE4A4)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW40_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW40_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_03 (0x83080000 + 0XE4A8)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_04 (0x83080000 + 0XE4AC)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW40_05 (0x83080000 + 0XE4B0)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW40_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW40_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW40_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_00 (0x83080000 + 0XE4B4)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_01 (0x83080000 + 0XE4B8)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_02 (0x83080000 + 0XE4BC)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW80_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW80_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_03 (0x83080000 + 0XE4C0)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_04 (0x83080000 + 0XE4C4)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW80_05 (0x83080000 + 0XE4C8)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW80_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW80_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW80_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_00 (0x83080000 + 0XE4CC)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_00_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_01 (0x83080000 + 0XE4D0)---

    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_01_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_02 (0x83080000 + 0XE4D4)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_BW160_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_02_CR_BAND_TPC_SKU2_FCC_BF_X_BW160_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_03 (0x83080000 + 0XE4D8)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_03_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_04 (0x83080000 + 0XE4DC)---

    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_04_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_BW160_05 (0x83080000 + 0XE4E0)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_BW160_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_BW160_05_CR_BAND_TPC_SKU2_FCC_BF_O_BW160_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_00 (0x83080000 + 0XE4E4)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_01 (0x83080000 + 0XE4E8)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_02 (0x83080000 + 0XE4EC)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU26_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU26_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_03 (0x83080000 + 0XE4F0)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_04 (0x83080000 + 0XE4F4)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU26_05 (0x83080000 + 0XE4F8)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU26_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU26_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU26_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_00 (0x83080000 + 0XE4FC)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_01 (0x83080000 + 0XE500)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_02 (0x83080000 + 0XE504)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU52_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU52_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_03 (0x83080000 + 0XE508)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_04 (0x83080000 + 0XE50c)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU52_05 (0x83080000 + 0XE510)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU52_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU52_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU52_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_00 (0x83080000 + 0XE514)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_00_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_01 (0x83080000 + 0XE518)---

    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_01_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_02 (0x83080000 + 0XE51C)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_RU106_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_02_CR_BAND_TPC_SKU2_FCC_BF_X_RU106_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_03 (0x83080000 + 0XE520)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_03_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_04 (0x83080000 + 0XE524)---

    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_3TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_2STS_4TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_3TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_3TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_04_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_3TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_RU106_05 (0x83080000 + 0XE528)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_4STS_4TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_4TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_4TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_4TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_3STS_4TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_4STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_4STS_4TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_RU106_4STS_4TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_RU106_05_CR_BAND_TPC_SKU2_FCC_BF_O_RU106_4STS_4TX_SHFT 16

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00 (0x83080000 + 0XE52C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01 (0x83080000 + 0XE530)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00 (0x83080000 + 0XE534)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01 (0x83080000 + 0XE538)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00 (0x83080000 + 0XE53C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU26_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01 (0x83080000 + 0XE540)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU26_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00 (0x83080000 + 0XE544)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01 (0x83080000 + 0XE548)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00 (0x83080000 + 0XE54C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01 (0x83080000 + 0XE550)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00 (0x83080000 + 0XE554)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW20_RU52_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01 (0x83080000 + 0XE558)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW20_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW20_RU52_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00 (0x83080000 + 0XE55C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01 (0x83080000 + 0XE560)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00 (0x83080000 + 0XE564)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01 (0x83080000 + 0XE568)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00 (0x83080000 + 0XE56C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU26_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01 (0x83080000 + 0XE570)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU26_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00 (0x83080000 + 0XE574)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01 (0x83080000 + 0XE578)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00 (0x83080000 + 0XE57C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01 (0x83080000 + 0XE580)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00 (0x83080000 + 0XE584)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU52_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01 (0x83080000 + 0XE588)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU52_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00 (0x83080000 + 0XE58C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01 (0x83080000 + 0XE590)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00 (0x83080000 + 0XE594)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01 (0x83080000 + 0XE598)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00 (0x83080000 + 0XE59C)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW40_RU106_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01 (0x83080000 + 0XE5A0)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW40_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW40_RU106_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00 (0x83080000 + 0XE5A4)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01 (0x83080000 + 0XE5A8)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00 (0x83080000 + 0XE5AC)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01 (0x83080000 + 0XE5B0)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00 (0x83080000 + 0XE5B4)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU26_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01 (0x83080000 + 0XE5B8)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU26_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU26_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00 (0x83080000 + 0XE5BC)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01 (0x83080000 + 0XE5C0)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00 (0x83080000 + 0XE5C4)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01 (0x83080000 + 0XE5C8)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00 (0x83080000 + 0XE700)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU52_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01 (0x83080000 + 0XE704)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU52_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU52_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00 (0x83080000 + 0XE708)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01 (0x83080000 + 0XE70C)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00 (0x83080000 + 0XE710)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01 (0x83080000 + 0XE714)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00 (0x83080000 + 0XE718)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU106_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01 (0x83080000 + 0XE71C)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU106_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU106_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00 (0x83080000 + 0XE720)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_L_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01 (0x83080000 + 0XE724)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_L_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_L_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00 (0x83080000 + 0XE728)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_R_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01 (0x83080000 + 0XE72C)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_R_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_R_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00 (0x83080000 + 0XE730)---

    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_4TX[7..0] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_3TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_2TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_1TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_1TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_1TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_1TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_1TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_2TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_2TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_2TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_3TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_3TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_3TX_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_4TX_MASK 0x000000FF                // CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_4TX[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_00_CR_BAND_TPC_SKU2_FCC_BF_X_DBW80_RU242_C_1STS_4TX_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01 (0x83080000 + 0XE734)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_4TX[15..8] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_3TX[23..16] - (RW) [DE] BBP control CR
    CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_2TX[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_2TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_2TX_MASK 0xFF000000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_2TX[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_2TX_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_3TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_3TX_MASK 0x00FF0000                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_3TX[23..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_3TX_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_4TX_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_4TX_MASK 0x0000FF00                // CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_4TX[15..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_SKU2_FCC_DBW80_RU242_C_01_CR_BAND_TPC_SKU2_FCC_BF_O_DBW80_RU242_C_1STS_4TX_SHFT 8

/* =====================================================================================

  ---CR_BAND_TPC_MCS_LG_00 (0x83080000 + 0XE738)---

    CR_BAND_TPC_MCS_LG_0[2..0]   - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_1[6..4]   - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_2[10..8]  - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_3[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_4[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_5[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_6[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_7[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_7_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_7_MASK 0x70000000                // CR_BAND_TPC_MCS_LG_7[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_7_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_6_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_6_MASK 0x07000000                // CR_BAND_TPC_MCS_LG_6[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_6_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_5_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_5_MASK 0x00700000                // CR_BAND_TPC_MCS_LG_5[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_5_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_4_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_4_MASK 0x00070000                // CR_BAND_TPC_MCS_LG_4[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_4_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_3_MASK 0x00007000                // CR_BAND_TPC_MCS_LG_3[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_3_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_2_MASK 0x00000700                // CR_BAND_TPC_MCS_LG_2[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_2_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_1_MASK 0x00000070                // CR_BAND_TPC_MCS_LG_1[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_1_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_0_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_0_MASK 0x00000007                // CR_BAND_TPC_MCS_LG_0[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_LG_00_CR_BAND_TPC_MCS_LG_0_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HT_00 (0x83080000 + 0XE73C)---

    CR_BAND_TPC_MCS_HT_24[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_25[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_26[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_27[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_28[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_29[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_30[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_31[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_31_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_31_MASK 0x70000000                // CR_BAND_TPC_MCS_HT_31[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_31_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_30_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_30_MASK 0x07000000                // CR_BAND_TPC_MCS_HT_30[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_30_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_29_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_29_MASK 0x00700000                // CR_BAND_TPC_MCS_HT_29[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_29_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_28_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_28_MASK 0x00070000                // CR_BAND_TPC_MCS_HT_28[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_28_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_27_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_27_MASK 0x00007000                // CR_BAND_TPC_MCS_HT_27[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_27_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_26_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_26_MASK 0x00000700                // CR_BAND_TPC_MCS_HT_26[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_26_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_25_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_25_MASK 0x00000070                // CR_BAND_TPC_MCS_HT_25[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_25_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_24_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_24_MASK 0x00000007                // CR_BAND_TPC_MCS_HT_24[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_00_CR_BAND_TPC_MCS_HT_24_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HT_01 (0x83080000 + 0XE740)---

    CR_BAND_TPC_MCS_HT_16[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_17[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_18[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_19[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_20[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_21[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_22[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_23[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_23_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_23_MASK 0x70000000                // CR_BAND_TPC_MCS_HT_23[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_23_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_22_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_22_MASK 0x07000000                // CR_BAND_TPC_MCS_HT_22[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_22_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_21_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_21_MASK 0x00700000                // CR_BAND_TPC_MCS_HT_21[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_21_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_20_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_20_MASK 0x00070000                // CR_BAND_TPC_MCS_HT_20[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_20_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_19_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_19_MASK 0x00007000                // CR_BAND_TPC_MCS_HT_19[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_19_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_18_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_18_MASK 0x00000700                // CR_BAND_TPC_MCS_HT_18[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_18_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_17_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_17_MASK 0x00000070                // CR_BAND_TPC_MCS_HT_17[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_17_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_16_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_16_MASK 0x00000007                // CR_BAND_TPC_MCS_HT_16[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_01_CR_BAND_TPC_MCS_HT_16_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HT_02 (0x83080000 + 0XE744)---

    CR_BAND_TPC_MCS_HT_08[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_09[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_10[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_11[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_12[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_13[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_14[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_15[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_15_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_15_MASK 0x70000000                // CR_BAND_TPC_MCS_HT_15[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_15_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_14_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_14_MASK 0x07000000                // CR_BAND_TPC_MCS_HT_14[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_14_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_13_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_13_MASK 0x00700000                // CR_BAND_TPC_MCS_HT_13[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_13_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_12_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_12_MASK 0x00070000                // CR_BAND_TPC_MCS_HT_12[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_12_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_11_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_11_MASK 0x00007000                // CR_BAND_TPC_MCS_HT_11[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_11_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_10_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_10_MASK 0x00000700                // CR_BAND_TPC_MCS_HT_10[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_10_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_09_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_09_MASK 0x00000070                // CR_BAND_TPC_MCS_HT_09[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_09_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_08_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_08_MASK 0x00000007                // CR_BAND_TPC_MCS_HT_08[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_02_CR_BAND_TPC_MCS_HT_08_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HT_03 (0x83080000 + 0XE748)---

    CR_BAND_TPC_MCS_HT_00[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_01[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_02[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_03[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_04[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_05[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_06[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HT_07[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_07_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_07_MASK 0x70000000                // CR_BAND_TPC_MCS_HT_07[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_07_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_06_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_06_MASK 0x07000000                // CR_BAND_TPC_MCS_HT_06[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_06_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_05_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_05_MASK 0x00700000                // CR_BAND_TPC_MCS_HT_05[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_05_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_04_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_04_MASK 0x00070000                // CR_BAND_TPC_MCS_HT_04[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_04_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_03_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_03_MASK 0x00007000                // CR_BAND_TPC_MCS_HT_03[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_03_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_02_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_02_MASK 0x00000700                // CR_BAND_TPC_MCS_HT_02[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_02_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_01_MASK 0x00000070                // CR_BAND_TPC_MCS_HT_01[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_01_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_00_MASK 0x00000007                // CR_BAND_TPC_MCS_HT_00[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HT_03_CR_BAND_TPC_MCS_HT_00_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_VHT_00 (0x83080000 + 0XE74C)---

    CR_BAND_TPC_MCS_VHT_08[2..0] - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_09[6..4] - (RW) [DE] BBP control CR
    RESERVED7[31..7]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_09_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_09_MASK 0x00000070                // CR_BAND_TPC_MCS_VHT_09[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_09_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_08_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_08_MASK 0x00000007                // CR_BAND_TPC_MCS_VHT_08[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_00_CR_BAND_TPC_MCS_VHT_08_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_VHT_01 (0x83080000 + 0XE750)---

    CR_BAND_TPC_MCS_VHT_00[2..0] - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_01[6..4] - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_02[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_03[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_04[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_05[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_06[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_VHT_07[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_07_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_07_MASK 0x70000000                // CR_BAND_TPC_MCS_VHT_07[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_07_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_06_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_06_MASK 0x07000000                // CR_BAND_TPC_MCS_VHT_06[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_06_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_05_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_05_MASK 0x00700000                // CR_BAND_TPC_MCS_VHT_05[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_05_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_04_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_04_MASK 0x00070000                // CR_BAND_TPC_MCS_VHT_04[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_04_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_03_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_03_MASK 0x00007000                // CR_BAND_TPC_MCS_VHT_03[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_03_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_02_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_02_MASK 0x00000700                // CR_BAND_TPC_MCS_VHT_02[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_02_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_01_MASK 0x00000070                // CR_BAND_TPC_MCS_VHT_01[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_01_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_00_MASK 0x00000007                // CR_BAND_TPC_MCS_VHT_00[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_VHT_01_CR_BAND_TPC_MCS_VHT_00_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HE_00 (0x83080000 + 0XE754)---

    CR_BAND_TPC_MCS_HE_08[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_09[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_10[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_11[14..12] - (RW) [DE] BBP control CR
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_11_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_11_MASK 0x00007000                // CR_BAND_TPC_MCS_HE_11[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_11_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_10_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_10_MASK 0x00000700                // CR_BAND_TPC_MCS_HE_10[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_10_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_09_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_09_MASK 0x00000070                // CR_BAND_TPC_MCS_HE_09[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_09_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_08_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_08_MASK 0x00000007                // CR_BAND_TPC_MCS_HE_08[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_00_CR_BAND_TPC_MCS_HE_08_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_HE_01 (0x83080000 + 0XE758)---

    CR_BAND_TPC_MCS_HE_00[2..0]  - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_01[6..4]  - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_02[10..8] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_03[14..12] - (RW) [DE] BBP control CR
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_04[18..16] - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_05[22..20] - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_06[26..24] - (RW) [DE] BBP control CR
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TPC_MCS_HE_07[30..28] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_07_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_07_MASK 0x70000000                // CR_BAND_TPC_MCS_HE_07[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_07_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_06_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_06_MASK 0x07000000                // CR_BAND_TPC_MCS_HE_06[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_06_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_05_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_05_MASK 0x00700000                // CR_BAND_TPC_MCS_HE_05[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_05_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_04_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_04_MASK 0x00070000                // CR_BAND_TPC_MCS_HE_04[18..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_04_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_03_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_03_MASK 0x00007000                // CR_BAND_TPC_MCS_HE_03[14..12]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_03_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_02_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_02_MASK 0x00000700                // CR_BAND_TPC_MCS_HE_02[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_02_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_01_MASK 0x00000070                // CR_BAND_TPC_MCS_HE_01[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_01_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_00_MASK 0x00000007                // CR_BAND_TPC_MCS_HE_00[2..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_HE_01_CR_BAND_TPC_MCS_HE_00_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_MCS_CTL_00 (0x83080000 + 0XE75C)---

    RESERVED0[22..0]             - (RO) Reserved bits
    CR_BAND_TPC_MCS_LG_HT_TX_RATE_MAX_GATE[23] - (RW) [DE] BBP control CR
    CR_BAND_TPC_MCS_HIGH_LOW_RATE[26..24] - (RW) [DE] BBP control CR
    RESERVED27[30..27]           - (RO) Reserved bits
    CR_BAND_TPC_MCS_HIGH_LOW_RATE_MAN[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_MAN_MASK 0x80000000                // CR_BAND_TPC_MCS_HIGH_LOW_RATE_MAN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_MAN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_MASK 0x07000000                // CR_BAND_TPC_MCS_HIGH_LOW_RATE[26..24]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_HIGH_LOW_RATE_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_LG_HT_TX_RATE_MAX_GATE_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_LG_HT_TX_RATE_MAX_GATE_MASK 0x00800000                // CR_BAND_TPC_MCS_LG_HT_TX_RATE_MAX_GATE[23]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_MCS_CTL_00_CR_BAND_TPC_MCS_LG_HT_TX_RATE_MAX_GATE_SHFT 23

/* =====================================================================================

  ---CR_BAND_TPC_RSVD_00 (0x83080000 + 0XE798)---

    CR_BAND_TPC_RSVD_00[31..0]   - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_00_CR_BAND_TPC_RSVD_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_00_CR_BAND_TPC_RSVD_00_MASK 0xFFFFFFFF                // CR_BAND_TPC_RSVD_00[31..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_00_CR_BAND_TPC_RSVD_00_SHFT 0

/* =====================================================================================

  ---CR_BAND_TPC_RSVD_01 (0x83080000 + 0XE79C)---

    CR_BAND_TPC_RSVD_01[31..0]   - (RW) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_01_CR_BAND_TPC_RSVD_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_01_CR_BAND_TPC_RSVD_01_MASK 0xFFFFFFFF                // CR_BAND_TPC_RSVD_01[31..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TPC_RSVD_01_CR_BAND_TPC_RSVD_01_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_00 (0x83080000 + 0XE7A0)---

    RO_BAND_TPC_CTRL_STAT_00[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_00_RO_BAND_TPC_CTRL_STAT_00_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_00_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_00_RO_BAND_TPC_CTRL_STAT_00_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_00[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_00_RO_BAND_TPC_CTRL_STAT_00_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_01 (0x83080000 + 0XE7A4)---

    RO_BAND_TPC_CTRL_STAT_01[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_01_RO_BAND_TPC_CTRL_STAT_01_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_01_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_01_RO_BAND_TPC_CTRL_STAT_01_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_01[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_01_RO_BAND_TPC_CTRL_STAT_01_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_02 (0x83080000 + 0XE7A8)---

    RO_BAND_TPC_CTRL_STAT_02[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_02_RO_BAND_TPC_CTRL_STAT_02_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_02_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_02_RO_BAND_TPC_CTRL_STAT_02_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_02[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_02_RO_BAND_TPC_CTRL_STAT_02_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_03 (0x83080000 + 0XE7AC)---

    RO_BAND_TPC_CTRL_STAT_03[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_03_RO_BAND_TPC_CTRL_STAT_03_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_03_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_03_RO_BAND_TPC_CTRL_STAT_03_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_03[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_03_RO_BAND_TPC_CTRL_STAT_03_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_04 (0x83080000 + 0XE7B0)---

    RO_BAND_TPC_CTRL_STAT_04[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_04_RO_BAND_TPC_CTRL_STAT_04_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_04_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_04_RO_BAND_TPC_CTRL_STAT_04_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_04[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_04_RO_BAND_TPC_CTRL_STAT_04_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_05 (0x83080000 + 0XE7B4)---

    RO_BAND_TPC_CTRL_STAT_05[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_05_RO_BAND_TPC_CTRL_STAT_05_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_05_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_05_RO_BAND_TPC_CTRL_STAT_05_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_05[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_05_RO_BAND_TPC_CTRL_STAT_05_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_06 (0x83080000 + 0XE7B8)---

    RO_BAND_TPC_CTRL_STAT_06[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_06_RO_BAND_TPC_CTRL_STAT_06_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_06_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_06_RO_BAND_TPC_CTRL_STAT_06_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_06[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_06_RO_BAND_TPC_CTRL_STAT_06_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_07 (0x83080000 + 0XE7BC)---

    RO_BAND_TPC_CTRL_STAT_07[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_07_RO_BAND_TPC_CTRL_STAT_07_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_07_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_07_RO_BAND_TPC_CTRL_STAT_07_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_07[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_07_RO_BAND_TPC_CTRL_STAT_07_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_08 (0x83080000 + 0XE7C0)---

    RO_BAND_TPC_CTRL_STAT_08[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_08_RO_BAND_TPC_CTRL_STAT_08_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_08_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_08_RO_BAND_TPC_CTRL_STAT_08_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_08[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_08_RO_BAND_TPC_CTRL_STAT_08_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_09 (0x83080000 + 0XE7C4)---

    RO_BAND_TPC_CTRL_STAT_09[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_09_RO_BAND_TPC_CTRL_STAT_09_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_09_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_09_RO_BAND_TPC_CTRL_STAT_09_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_09[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_09_RO_BAND_TPC_CTRL_STAT_09_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_10 (0x83080000 + 0XE7C8)---

    RO_BAND_TPC_CTRL_STAT_10[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_10_RO_BAND_TPC_CTRL_STAT_10_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_10_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_10_RO_BAND_TPC_CTRL_STAT_10_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_10[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_10_RO_BAND_TPC_CTRL_STAT_10_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_11 (0x83080000 + 0XE7CC)---

    RO_BAND_TPC_CTRL_STAT_11[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_11_RO_BAND_TPC_CTRL_STAT_11_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_11_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_11_RO_BAND_TPC_CTRL_STAT_11_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_11[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_11_RO_BAND_TPC_CTRL_STAT_11_SHFT 0

/* =====================================================================================

  ---RO_BAND_TPC_CTRL_STAT_12 (0x83080000 + 0XE7D0)---

    RO_BAND_TPC_CTRL_STAT_12[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_12_RO_BAND_TPC_CTRL_STAT_12_ADDR BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_12_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_12_RO_BAND_TPC_CTRL_STAT_12_MASK 0xFFFFFFFF                // RO_BAND_TPC_CTRL_STAT_12[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TPC_CTRL_STAT_12_RO_BAND_TPC_CTRL_STAT_12_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_DCOC (0x83080000 + 0xF000)---

    CR_BAND_RXADC_CAL_EN[0]      - (RW) rxadc cal enable
    CR_BAND_RXADC_DIV_VLD_SEL[2..1] - (RW) ADC div valid selection
    CR_BAND_RXADC_DIV_VLD_EN[3]  - (RW) ADC div valid selection enbale
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_EN_MASK 0x00000008                // CR_BAND_RXADC_DIV_VLD_EN[3]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_EN_SHFT 3
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_SEL_MASK 0x00000006                // CR_BAND_RXADC_DIV_VLD_SEL[2..1]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_DIV_VLD_SEL_SHFT 1
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_CAL_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_CAL_EN_MASK 0x00000001                // CR_BAND_RXADC_CAL_EN[0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_DCOC_CR_BAND_RXADC_CAL_EN_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_VRCF_00_B0 (0x83080000 + 0xF004)---

    CR_BAND_VRCF_R[22..0]        - (RW) VRCF ratio
    CR_BAND_VRCF_PRVT_OVFL[23]   - (RW) prevent overflow happen for FIFO if VRCF always on
    CR_BAND_VRCF_ADDR_LOW[27..24] - (RW) lower bound for FIFO addr difference
    CR_BAND_VRCF_ADDR_UP[31..28] - (RW) upper bound for FIFO addr difference

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_UP_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_UP_MASK 0xF0000000                // CR_BAND_VRCF_ADDR_UP[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_UP_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_LOW_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_LOW_MASK 0x0F000000                // CR_BAND_VRCF_ADDR_LOW[27..24]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_ADDR_LOW_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_PRVT_OVFL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_PRVT_OVFL_MASK 0x00800000                // CR_BAND_VRCF_PRVT_OVFL[23]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_PRVT_OVFL_SHFT 23
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_R_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_R_MASK 0x007FFFFF                // CR_BAND_VRCF_R[22..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_00_B0_CR_BAND_VRCF_R_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_VRCF_01_B0 (0x83080000 + 0xF008)---

    CR_BAND_VRCF_R_DELTA[3..0]   - (RW) delta value for vrcf_r
    CR_BAND_DGC_GAIN_DB_VLD_FORCE_HIGH[4] - (RW) force dgc_gain_db_vld to always 1
    CR_BAND_RUNOTCH_IN_SEL_FD_OUT[5] - (RW) RU Notch always select FDIQC comp out
    CR_BAND_IB_AMP_IN_SEL[7..6]  - (RW) AGC IB AMP IN Selection
                                     2'b11: FI_COMP_OUT
                                     2'b10: FD_COMP_OUT
                                     2'b01: IQC_IN
                                     2'b00: RU Notch In
    RESERVED8[8]                 - (RO) Reserved bits
    CR_BAND_RXFE_TSSI_FALL_REV[9] - (RW) TSSI Enable falling value invert
    CR_BAND_RXFE_TSSI_RISE_REV[10] - (RW) TSSI Enable Rising value invert
    CR_BAND_DIS_TSSI_DCRF_BYPASS[11] - (RW) Disable TSSI Bypass DCRF
    CR_BAND_DIS_TSSI_VRCF_OFF[12] - (RW) Disable TSSI Turn off VRCF
    CR_BAND_PRESERVE_FOR_ECO[31..13] - (RW) RXFEpreseve

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_PRESERVE_FOR_ECO_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_PRESERVE_FOR_ECO_MASK 0xFFFFE000                // CR_BAND_PRESERVE_FOR_ECO[31..13]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_PRESERVE_FOR_ECO_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_VRCF_OFF_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_VRCF_OFF_MASK 0x00001000                // CR_BAND_DIS_TSSI_VRCF_OFF[12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_VRCF_OFF_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_DCRF_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_DCRF_BYPASS_MASK 0x00000800                // CR_BAND_DIS_TSSI_DCRF_BYPASS[11]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DIS_TSSI_DCRF_BYPASS_SHFT 11
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_RISE_REV_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_RISE_REV_MASK 0x00000400                // CR_BAND_RXFE_TSSI_RISE_REV[10]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_RISE_REV_SHFT 10
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_FALL_REV_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_FALL_REV_MASK 0x00000200                // CR_BAND_RXFE_TSSI_FALL_REV[9]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RXFE_TSSI_FALL_REV_SHFT 9
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_IB_AMP_IN_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_IB_AMP_IN_SEL_MASK 0x000000C0                // CR_BAND_IB_AMP_IN_SEL[7..6]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_IB_AMP_IN_SEL_SHFT 6
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RUNOTCH_IN_SEL_FD_OUT_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RUNOTCH_IN_SEL_FD_OUT_MASK 0x00000020                // CR_BAND_RUNOTCH_IN_SEL_FD_OUT[5]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_RUNOTCH_IN_SEL_FD_OUT_SHFT 5
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DGC_GAIN_DB_VLD_FORCE_HIGH_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DGC_GAIN_DB_VLD_FORCE_HIGH_MASK 0x00000010                // CR_BAND_DGC_GAIN_DB_VLD_FORCE_HIGH[4]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_DGC_GAIN_DB_VLD_FORCE_HIGH_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_VRCF_R_DELTA_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_VRCF_R_DELTA_MASK 0x0000000F                // CR_BAND_VRCF_R_DELTA[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_01_B0_CR_BAND_VRCF_R_DELTA_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_VRCF_02_B0 (0x83080000 + 0xF00C)---

    CR_BAND_VRCF_U_ACC_INIT[22..0] - (RW) set initial u value for VRCF bit-true
    RESERVED23[31..23]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_02_B0_CR_BAND_VRCF_U_ACC_INIT_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_02_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_02_B0_CR_BAND_VRCF_U_ACC_INIT_MASK 0x007FFFFF                // CR_BAND_VRCF_U_ACC_INIT[22..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_VRCF_02_B0_CR_BAND_VRCF_U_ACC_INIT_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_00_B0 (0x83080000 + 0xF010)---

    CR_BAND_FORCE_NOTCH_MODE_BEF_PD[0] - (RW) enable force notch mode for testing _BEF_PD
    CR_BAND_NOTCH_TYPE_BEF_PD[2..1] - (RW) notch type _BEF_PD
                                     2'b00 : only 1 one-pole notch
                                     2'b01 : 2 one-pole notch
                                     2'b10 : two-pole notch
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND_FORCE_NOTCH_MODE_AFT_PD[4] - (RW) enable force notch mode for testing _AFT_PD
    CR_BAND_NOTCH_TYPE_AFT_PD[6..5] - (RW) notch type _AFT_PD
                                     2'b00 : only 1 one-pole notch
                                     2'b01 : 2 one-pole notch
                                     2'b10 : two-pole notch
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_NOTCH_SEL_ED_THR[10..8] - (RW) ED threshold selection
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_NOTCH_SEL_ISR_THR1[17..12] - (RW) ISR function threshold1, -43~20 dB
    RESERVED18[19..18]           - (RO) Reserved bits
    CR_BAND_NOTCH_SEL_ISR_THR2[25..20] - (RW) ISR function threshold2, -103~-40 dB
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_BAND_NOTCH_MAN_ON_1[28]   - (RW) notch 1 on manual mode control
    CR_BAND_NOTCH_MAN_ON_CTL_1[29] - (RW) notch 1 on manual mode control enable
    CR_BAND_NOTCH_MAN_ON_2[30]   - (RW) notch 2 on manual mode control
    CR_BAND_NOTCH_MAN_ON_CTL_2[31] - (RW) notch 2 on manual mode control enable

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_2_MASK 0x80000000                // CR_BAND_NOTCH_MAN_ON_CTL_2[31]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_2_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_2_MASK 0x40000000                // CR_BAND_NOTCH_MAN_ON_2[30]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_2_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_1_MASK 0x20000000                // CR_BAND_NOTCH_MAN_ON_CTL_1[29]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_CTL_1_SHFT 29
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_1_MASK 0x10000000                // CR_BAND_NOTCH_MAN_ON_1[28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_MAN_ON_1_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR2_MASK 0x03F00000                // CR_BAND_NOTCH_SEL_ISR_THR2[25..20]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR2_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR1_MASK 0x0003F000                // CR_BAND_NOTCH_SEL_ISR_THR1[17..12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ISR_THR1_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ED_THR_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ED_THR_MASK 0x00000700                // CR_BAND_NOTCH_SEL_ED_THR[10..8]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_SEL_ED_THR_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_AFT_PD_MASK 0x00000060                // CR_BAND_NOTCH_TYPE_AFT_PD[6..5]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_AFT_PD_SHFT 5
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_AFT_PD_MASK 0x00000010                // CR_BAND_FORCE_NOTCH_MODE_AFT_PD[4]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_AFT_PD_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_BEF_PD_MASK 0x00000006                // CR_BAND_NOTCH_TYPE_BEF_PD[2..1]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_NOTCH_TYPE_BEF_PD_SHFT 1
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_BEF_PD_MASK 0x00000001                // CR_BAND_FORCE_NOTCH_MODE_BEF_PD[0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_00_B0_CR_BAND_FORCE_NOTCH_MODE_BEF_PD_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_01 (0x83080000 + 0xF014)---

    RESERVED0[9..0]              - (RO) Reserved bits
    CR_BAND_NOTCH1_R1_SET0[11..10] - (RW) notch 1 R1 value
    RESERVED12[21..12]           - (RO) Reserved bits
    CR_BAND_NOTCH1_R2_SET0[23..22] - (RW) notch 1 R2 value
    CR_BAND_NOTCH2_R1_SET0[25..24] - (RW) notch 2 R1 value
    CR_BAND_NOTCH2_R2_SET0[27..26] - (RW) notch 2 R2 value
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R2_SET0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R2_SET0_MASK 0x0C000000                // CR_BAND_NOTCH2_R2_SET0[27..26]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R2_SET0_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R1_SET0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R1_SET0_MASK 0x03000000                // CR_BAND_NOTCH2_R1_SET0[25..24]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH2_R1_SET0_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R2_SET0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R2_SET0_MASK 0x00C00000                // CR_BAND_NOTCH1_R2_SET0[23..22]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R2_SET0_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R1_SET0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R1_SET0_MASK 0x00000C00                // CR_BAND_NOTCH1_R1_SET0[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_01_CR_BAND_NOTCH1_R1_SET0_SHFT 10

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_02 (0x83080000 + 0xF018)---

    RESERVED0[9..0]              - (RO) Reserved bits
    CR_BAND_NOTCH1_R1_SET1[11..10] - (RW) notch 1 R1 value
    RESERVED12[21..12]           - (RO) Reserved bits
    CR_BAND_NOTCH1_R2_SET1[23..22] - (RW) notch 1 R2 value
    RESERVED24[27..24]           - (RO) Reserved bits
    CR_BAND_NOTCH_FC_DELTA_SET1[31..28] - (RW) center freq. set for manually control notch mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH_FC_DELTA_SET1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH_FC_DELTA_SET1_MASK 0xF0000000                // CR_BAND_NOTCH_FC_DELTA_SET1[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH_FC_DELTA_SET1_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R2_SET1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R2_SET1_MASK 0x00C00000                // CR_BAND_NOTCH1_R2_SET1[23..22]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R2_SET1_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R1_SET1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R1_SET1_MASK 0x00000C00                // CR_BAND_NOTCH1_R1_SET1[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_02_CR_BAND_NOTCH1_R1_SET1_SHFT 10

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_03 (0x83080000 + 0xF01C)---

    RESERVED0[9..0]              - (RO) Reserved bits
    CR_BAND_NOTCH1_R1_SET2[11..10] - (RW) notch 1 R1 value
    RESERVED12[21..12]           - (RO) Reserved bits
    CR_BAND_NOTCH1_R2_SET2[23..22] - (RW) notch 1 R2 value
    RESERVED24[27..24]           - (RO) Reserved bits
    CR_BAND_NOTCH_FC_DELTA_SET2[31..28] - (RW) center freq. set for manually control notch mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH_FC_DELTA_SET2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH_FC_DELTA_SET2_MASK 0xF0000000                // CR_BAND_NOTCH_FC_DELTA_SET2[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH_FC_DELTA_SET2_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R2_SET2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R2_SET2_MASK 0x00C00000                // CR_BAND_NOTCH1_R2_SET2[23..22]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R2_SET2_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R1_SET2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R1_SET2_MASK 0x00000C00                // CR_BAND_NOTCH1_R1_SET2[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_03_CR_BAND_NOTCH1_R1_SET2_SHFT 10

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_04 (0x83080000 + 0xF020)---

    CR_BAND_NOTCH_CENTER1_BEF_PD[9..0] - (RW) center freq. of notch 1 for force mode of before PD
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_BAND_NOTCH_CENTER2_BEF_PD[21..12] - (RW) center freq. of notch 2 for force mode of before PD
    RESERVED22[27..22]           - (RO) Reserved bits
    CR_BAND_NOTCH_FC_DELTA_BEF_PD[31..28] - (RW) center freq. set for manually control notch mode of before PD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_FC_DELTA_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_FC_DELTA_BEF_PD_MASK 0xF0000000                // CR_BAND_NOTCH_FC_DELTA_BEF_PD[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_FC_DELTA_BEF_PD_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER2_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER2_BEF_PD_MASK 0x003FF000                // CR_BAND_NOTCH_CENTER2_BEF_PD[21..12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER2_BEF_PD_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER1_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER1_BEF_PD_MASK 0x000003FF                // CR_BAND_NOTCH_CENTER1_BEF_PD[9..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_04_CR_BAND_NOTCH_CENTER1_BEF_PD_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_NOTCH_05 (0x83080000 + 0xF024)---

    CR_BAND_NOTCH_CENTER1_AFT_PD[9..0] - (RW) center freq. of notch 1 for force mode of afte PD
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_BAND_NOTCH_CENTER2_AFT_PD[21..12] - (RW) center freq. of notch 2 for force mode of afte PD
    RESERVED22[27..22]           - (RO) Reserved bits
    CR_BAND_NOTCH_FC_DELTA_AFT_PD[31..28] - (RW) center freq. set for manually control notch mode of afte PD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_FC_DELTA_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_FC_DELTA_AFT_PD_MASK 0xF0000000                // CR_BAND_NOTCH_FC_DELTA_AFT_PD[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_FC_DELTA_AFT_PD_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER2_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER2_AFT_PD_MASK 0x003FF000                // CR_BAND_NOTCH_CENTER2_AFT_PD[21..12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER2_AFT_PD_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER1_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER1_AFT_PD_MASK 0x000003FF                // CR_BAND_NOTCH_CENTER1_AFT_PD[9..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_NOTCH_05_CR_BAND_NOTCH_CENTER1_AFT_PD_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_00 (0x83080000 + 0xF028)---

    CR_BAND_DLPF_SEN160COEF_1[10..0] - (RW) DLPF coefficient : SEN
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_SEN160COEF_0[26..16] - (RW) DLPF coefficient : SEN
    RESERVED27[29..27]           - (RO) Reserved bits
    CR_BAND_DLPF_SA_SEL_AFT_PD[30] - (RW) DLPF coefficient shift-add mode
    CR_BAND_DLPF_SA_SEL_BEF_PD[31] - (RW) DLPF coefficient shift-add mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_BEF_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_BEF_PD_MASK 0x80000000                // CR_BAND_DLPF_SA_SEL_BEF_PD[31]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_BEF_PD_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_AFT_PD_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_AFT_PD_MASK 0x40000000                // CR_BAND_DLPF_SA_SEL_AFT_PD[30]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SA_SEL_AFT_PD_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_0_MASK 0x07FF0000                // CR_BAND_DLPF_SEN160COEF_0[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_0_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_1_MASK 0x000007FF                // CR_BAND_DLPF_SEN160COEF_1[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_00_CR_BAND_DLPF_SEN160COEF_1_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_01 (0x83080000 + 0xF02C)---

    CR_BAND_DLPF_SEN160COEF_3[10..0] - (RW) DLPF coefficient : SEN
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_SEN160COEF_2[26..16] - (RW) DLPF coefficient : SEN
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_2_MASK 0x07FF0000                // CR_BAND_DLPF_SEN160COEF_2[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_2_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_3_MASK 0x000007FF                // CR_BAND_DLPF_SEN160COEF_3[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_01_CR_BAND_DLPF_SEN160COEF_3_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_02 (0x83080000 + 0xF030)---

    CR_BAND_DLPF_SEN160COEF_5[10..0] - (RW) DLPF coefficient : SEN
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_SEN160COEF_4[26..16] - (RW) DLPF coefficient : SEN
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_4_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_4_MASK 0x07FF0000                // CR_BAND_DLPF_SEN160COEF_4[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_4_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_5_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_5_MASK 0x000007FF                // CR_BAND_DLPF_SEN160COEF_5[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_02_CR_BAND_DLPF_SEN160COEF_5_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_03 (0x83080000 + 0xF034)---

    CR_BAND_DLPF_SEN160COEF_7[10..0] - (RW) DLPF coefficient : SEN
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_SEN160COEF_6[26..16] - (RW) DLPF coefficient : SEN
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_6_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_6_MASK 0x07FF0000                // CR_BAND_DLPF_SEN160COEF_6[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_6_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_7_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_7_MASK 0x000007FF                // CR_BAND_DLPF_SEN160COEF_7[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_03_CR_BAND_DLPF_SEN160COEF_7_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_04 (0x83080000 + 0xF038)---

    CR_BAND_DLPF_ACI160COEF_0[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_SEN160COEF_8[26..16] - (RW) DLPF coefficient : SEN
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_SEN160COEF_8_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_SEN160COEF_8_MASK 0x07FF0000                // CR_BAND_DLPF_SEN160COEF_8[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_SEN160COEF_8_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_ACI160COEF_0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_ACI160COEF_0_MASK 0x000007FF                // CR_BAND_DLPF_ACI160COEF_0[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_04_CR_BAND_DLPF_ACI160COEF_0_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_05 (0x83080000 + 0xF03C)---

    CR_BAND_DLPF_ACI160COEF_2[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACI160COEF_1[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_1_MASK 0x07FF0000                // CR_BAND_DLPF_ACI160COEF_1[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_1_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_2_MASK 0x000007FF                // CR_BAND_DLPF_ACI160COEF_2[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_05_CR_BAND_DLPF_ACI160COEF_2_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_06 (0x83080000 + 0xF040)---

    CR_BAND_DLPF_ACI160COEF_4[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACI160COEF_3[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_3_MASK 0x07FF0000                // CR_BAND_DLPF_ACI160COEF_3[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_3_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_4_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_4_MASK 0x000007FF                // CR_BAND_DLPF_ACI160COEF_4[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_06_CR_BAND_DLPF_ACI160COEF_4_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_07 (0x83080000 + 0xF044)---

    CR_BAND_DLPF_ACI160COEF_6[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACI160COEF_5[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_5_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_5_MASK 0x07FF0000                // CR_BAND_DLPF_ACI160COEF_5[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_5_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_6_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_6_MASK 0x000007FF                // CR_BAND_DLPF_ACI160COEF_6[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_07_CR_BAND_DLPF_ACI160COEF_6_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_08 (0x83080000 + 0xF048)---

    CR_BAND_DLPF_ACI160COEF_8[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACI160COEF_7[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_7_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_7_MASK 0x07FF0000                // CR_BAND_DLPF_ACI160COEF_7[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_7_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_8_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_8_MASK 0x000007FF                // CR_BAND_DLPF_ACI160COEF_8[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_08_CR_BAND_DLPF_ACI160COEF_8_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_09 (0x83080000 + 0xF04C)---

    CR_BAND_DLPF_ACIAXCOEF_1[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACIAXCOEF_0[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_0_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_0_MASK 0x07FF0000                // CR_BAND_DLPF_ACIAXCOEF_0[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_0_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_1_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_1_MASK 0x000007FF                // CR_BAND_DLPF_ACIAXCOEF_1[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_09_CR_BAND_DLPF_ACIAXCOEF_1_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_10 (0x83080000 + 0xF050)---

    CR_BAND_DLPF_ACIAXCOEF_3[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACIAXCOEF_2[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_2_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_2_MASK 0x07FF0000                // CR_BAND_DLPF_ACIAXCOEF_2[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_2_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_3_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_3_MASK 0x000007FF                // CR_BAND_DLPF_ACIAXCOEF_3[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_10_CR_BAND_DLPF_ACIAXCOEF_3_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_11 (0x83080000 + 0xF054)---

    CR_BAND_DLPF_ACIAXCOEF_5[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACIAXCOEF_4[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_4_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_4_MASK 0x07FF0000                // CR_BAND_DLPF_ACIAXCOEF_4[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_4_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_5_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_5_MASK 0x000007FF                // CR_BAND_DLPF_ACIAXCOEF_5[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_11_CR_BAND_DLPF_ACIAXCOEF_5_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_12 (0x83080000 + 0xF058)---

    CR_BAND_DLPF_ACIAXCOEF_7[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_DLPF_ACIAXCOEF_6[26..16] - (RW) DLPF coefficient : ACI
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_6_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_6_MASK 0x07FF0000                // CR_BAND_DLPF_ACIAXCOEF_6[26..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_6_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_7_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_7_MASK 0x000007FF                // CR_BAND_DLPF_ACIAXCOEF_7[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_12_CR_BAND_DLPF_ACIAXCOEF_7_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_DLPF_13 (0x83080000 + 0xF05C)---

    CR_BAND_DLPF_ACIAXCOEF_8[10..0] - (RW) DLPF coefficient : ACI
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND_ACIF_SMALL_ISR_BW20[16] - (RW) DLPF sel ax coef when small isr 1/0 = sel ax coef/ac coef
    CR_BAND_ACIF_SMALL_ISR_BW40[17] - (RW) DLPF sel ax coef when small isr 1/0 = sel ax coef/ac coef
    CR_BAND_ACIF_SMALL_ISR_BW80[18] - (RW) DLPF sel ax coef when small isr 1/0 = sel ax coef/ac coef
    RESERVED19[31..19]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW80_MASK 0x00040000                // CR_BAND_ACIF_SMALL_ISR_BW80[18]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW80_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW40_MASK 0x00020000                // CR_BAND_ACIF_SMALL_ISR_BW40[17]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW40_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW20_MASK 0x00010000                // CR_BAND_ACIF_SMALL_ISR_BW20[16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_ACIF_SMALL_ISR_BW20_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_DLPF_ACIAXCOEF_8_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_DLPF_ACIAXCOEF_8_MASK 0x000007FF                // CR_BAND_DLPF_ACIAXCOEF_8[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_DLPF_13_CR_BAND_DLPF_ACIAXCOEF_8_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_IQC (0x83080000 + 0xF060)---

    CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW20[0] - (RW) Bypass IQC before PD
    CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW40[1] - (RW) Bypass IQC before PD
    CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW80[2] - (RW) Bypass IQC before PD
    CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160[3] - (RW) Bypass IQC before PD
    CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160NC[4] - (RW) Bypass IQC before PD
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160NC_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160NC_MASK 0x00000010                // CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160NC[4]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160NC_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160_MASK 0x00000008                // CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160[3]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW160_SHFT 3
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW80_MASK 0x00000004                // CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW80[2]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW80_SHFT 2
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW40_MASK 0x00000002                // CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW40[1]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW40_SHFT 1
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW20_MASK 0x00000001                // CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW20[0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_IQC_CR_BAND_BYPASS_FDIQ_COMP_NOPD_BW20_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_00 (0x83080000 + 0xF064)---

    CR_BAND_MANUAL_MODE_CTRL[0]  - (RW) manual mode control enable
    CR_BAND_RXFE_ON[1]           - (RW) manually turn on RXFE
    CR_BAND_RXFE_AFIFO_ONLY[2]   - (RW) only enable AFIFO for some calibration application
    CR_BAND_RXADC_CK_HOP[3]      - (RW) enable rxadc hopping for desense
    CR_BAND_RXFE_CBW[7..4]       - (RW) force channel bandwidth
    RESERVED8[9..8]              - (RO) Reserved bits
    CR_BAND_PKDT_RATE_MODE[11..10] - (RW) peak detect RATE MODE to AGC
    RESERVED12[13..12]           - (RO) Reserved bits
    CR_BAND_BYPASS_FIIQ_COMP[14] - (RW) bypass RXFIIQ compensation
    CR_BAND_IQCOUT_SEL[15]       - (RW) IQC output sel, set 0 is to bypass FDIQC
    CR_BAND_RXADC_IN_FORMAT[16]  - (RW) ADC input format conversion
    RESERVED17[17]               - (RO) Reserved bits
    CR_BAND_IQ_SWAP[18]          - (RW) IQ swap select
    CR_BAND_IQC_METHOD_SEL[19]   - (RW) IQC method, 1: RXFI->RXFD
                                     0: RXFD->RXFI
    CR_BAND_CCA_DC_EN[20]        - (RW) CCA_DC enable
    CR_BAND_CAPT_IQC_INPUT[21]   - (RW) capture mode IQC selection
    CR_BAND_FLAG_DATASEL[23..22] - (RW) flag selection of iqc related for debug
    CR_BAND_SYNC_RST_LEN[31..24] - (RW) Sync. reset length

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_SYNC_RST_LEN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_SYNC_RST_LEN_MASK 0xFF000000                // CR_BAND_SYNC_RST_LEN[31..24]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_SYNC_RST_LEN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_FLAG_DATASEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_FLAG_DATASEL_MASK 0x00C00000                // CR_BAND_FLAG_DATASEL[23..22]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_FLAG_DATASEL_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CAPT_IQC_INPUT_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CAPT_IQC_INPUT_MASK 0x00200000                // CR_BAND_CAPT_IQC_INPUT[21]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CAPT_IQC_INPUT_SHFT 21
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CCA_DC_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CCA_DC_EN_MASK 0x00100000                // CR_BAND_CCA_DC_EN[20]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_CCA_DC_EN_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQC_METHOD_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQC_METHOD_SEL_MASK 0x00080000                // CR_BAND_IQC_METHOD_SEL[19]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQC_METHOD_SEL_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQ_SWAP_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQ_SWAP_MASK 0x00040000                // CR_BAND_IQ_SWAP[18]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQ_SWAP_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_IN_FORMAT_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_IN_FORMAT_MASK 0x00010000                // CR_BAND_RXADC_IN_FORMAT[16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_IN_FORMAT_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQCOUT_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQCOUT_SEL_MASK 0x00008000                // CR_BAND_IQCOUT_SEL[15]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_IQCOUT_SEL_SHFT 15
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_BYPASS_FIIQ_COMP_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_BYPASS_FIIQ_COMP_MASK 0x00004000                // CR_BAND_BYPASS_FIIQ_COMP[14]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_BYPASS_FIIQ_COMP_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_PKDT_RATE_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_PKDT_RATE_MODE_MASK 0x00000C00                // CR_BAND_PKDT_RATE_MODE[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_PKDT_RATE_MODE_SHFT 10
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_CBW_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_CBW_MASK 0x000000F0                // CR_BAND_RXFE_CBW[7..4]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_CBW_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_CK_HOP_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_CK_HOP_MASK 0x00000008                // CR_BAND_RXADC_CK_HOP[3]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXADC_CK_HOP_SHFT 3
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_AFIFO_ONLY_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_AFIFO_ONLY_MASK 0x00000004                // CR_BAND_RXFE_AFIFO_ONLY[2]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_AFIFO_ONLY_SHFT 2
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_ON_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_ON_MASK 0x00000002                // CR_BAND_RXFE_ON[1]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_RXFE_ON_SHFT 1
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_MANUAL_MODE_CTRL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_MANUAL_MODE_CTRL_MASK 0x00000001                // CR_BAND_MANUAL_MODE_CTRL[0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_00_CR_BAND_MANUAL_MODE_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_01 (0x83080000 + 0xF068)---

    CR_BAND_MAN_DOWNSAMP[1..0]   - (RW) manual mode for ADC downsampling,0:no 1: downsamp by 2 2: downsamp by 4
    CR_BAND_RXFE_AFIFO_RD_EN[2]  - (RW) manual enable of AFIFO
    CR_BAND_RXFE_AFIFO_CK320M[3] - (RW) Set 1 when RX AFIFO use 320M clock
    CR_BAND_DLPF_MODE_MAN_CTL[5..4] - (RW) DLPF mode manual mode control (0 for SEN, 1 for ACI)
    CR_BAND_DLPF_MODE_MAN_EN[6]  - (RW) enable DLPF mode manual control
    CR_BAND_RXFE_DIS_ADC_FLT_RST[7] - (RW) let ADC douwnsample filters always on for TOAE
    CR_BAND_TSSI_BW[11..8]       - (RW) Referenced BW setting when under TSSI mode
    CR_BAND_WB_SEL[15..12]       - (RW) WB RSSI data to AGC CR mode selection
    CR_BAND_ADC480M_MODE[16]     - (RW) for 40/80/160 to indicate ADC under 480M clk
    RESERVED17[17]               - (RO) Reserved bits
    CR_BAND_DLPF_BW8080C_ACI_SEL[18] - (RW) when 8080c + ACI mode  0: use 29 tap 1:use ACI 19 tap coef
    CR_BAND_RXFE_DBG_SEL_RX[19]  - (RW) dbg rx sel Band0 : 0:rx0 1:rx1 Band1 :  0:rx2 1:rx3
    RESERVED20[25..20]           - (RO) Reserved bits
    CR_BAND_RXFDIQ_TAP_NUM[27..26] - (RW) RXFDIQ tap number -  0 : 15-tap , 1 : 17-tap , 2 : 19-tap
    CR_BAND_ADCDC_COMP_VAL[31..28] - (RW) ADC DC compensation manaul value, default is 0 but real chip should be 0.25

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADCDC_COMP_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADCDC_COMP_VAL_MASK 0xF0000000                // CR_BAND_ADCDC_COMP_VAL[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADCDC_COMP_VAL_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFDIQ_TAP_NUM_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFDIQ_TAP_NUM_MASK 0x0C000000                // CR_BAND_RXFDIQ_TAP_NUM[27..26]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFDIQ_TAP_NUM_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DBG_SEL_RX_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DBG_SEL_RX_MASK 0x00080000                // CR_BAND_RXFE_DBG_SEL_RX[19]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DBG_SEL_RX_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_BW8080C_ACI_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_BW8080C_ACI_SEL_MASK 0x00040000                // CR_BAND_DLPF_BW8080C_ACI_SEL[18]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_BW8080C_ACI_SEL_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADC480M_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADC480M_MODE_MASK 0x00010000                // CR_BAND_ADC480M_MODE[16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_ADC480M_MODE_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_WB_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_WB_SEL_MASK 0x0000F000                // CR_BAND_WB_SEL[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_WB_SEL_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_TSSI_BW_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_TSSI_BW_MASK 0x00000F00                // CR_BAND_TSSI_BW[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_TSSI_BW_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DIS_ADC_FLT_RST_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DIS_ADC_FLT_RST_MASK 0x00000080                // CR_BAND_RXFE_DIS_ADC_FLT_RST[7]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_DIS_ADC_FLT_RST_SHFT 7
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_EN_MASK 0x00000040                // CR_BAND_DLPF_MODE_MAN_EN[6]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_EN_SHFT 6
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_CTL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_CTL_MASK 0x00000030                // CR_BAND_DLPF_MODE_MAN_CTL[5..4]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_DLPF_MODE_MAN_CTL_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_CK320M_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_CK320M_MASK 0x00000008                // CR_BAND_RXFE_AFIFO_CK320M[3]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_CK320M_SHFT 3
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_RD_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_RD_EN_MASK 0x00000004                // CR_BAND_RXFE_AFIFO_RD_EN[2]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_RXFE_AFIFO_RD_EN_SHFT 2
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_MAN_DOWNSAMP_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_MAN_DOWNSAMP_MASK 0x00000003                // CR_BAND_MAN_DOWNSAMP[1..0]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_01_CR_BAND_MAN_DOWNSAMP_SHFT 0

/* =====================================================================================

  ---CR_BAND_WF_RXFE_02 (0x83080000 + 0xF06C)---

    RESERVED0[2..0]              - (RO) Reserved bits
    CR_BAND_VRCF_RST_DISABLE[3]  - (RW) disable vrcf rst function
    RESERVED4[4]                 - (RO) Reserved bits
    CR_BAND_IQC_RST_DISABLE[5]   - (RW) disable iqc rst function
    CR_BAND_DLPF_RST_DISABLE[6]  - (RW) disable dlpf rst function
    CR_BAND_AFIFO_WR_RST_DISABLE[7] - (RW) disable afifo write rst function
    CR_BAND_AFIFO_RD_RST_DISABLE[8] - (RW) disable afifo read rst function
    CR_BAND_SHARED_DBG_RX_SEL[9] - (RW) disable afifo read rst function
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_BAND_TSSI_MAN[12]         - (RW) TSSI enter manual mode to control CIC4 CIC5
    CR_BAND_TSSI_CIC5_EN[13]     - (RW) TSSI enter manual mode of CIC5
    CR_BAND_TSSI_CIC4_EN[14]     - (RW) TSSI enter manual mode of CIC4
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RFDGC_DEFAULT_GAIN[21..16] - (RW) RFDGC default gain @ adc domain
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_BAND_RFDGC_GAIN_FORCE_EN[24] - (RW) we use this bit to force RFDGC gain
    CR_BAND_RXFE_EN_SEL[25]      - (RW) rxfe_en rollback
    CR_BAND_RXFE_EN_SEPARATE[26] - (RW) rxfe_en separate (no and)
    CR_BAND_DGC_TSSI_ON_USE_EDGE[27] - (RW) RXFE DGC tssi on use posedge
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DGC_TSSI_ON_USE_EDGE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DGC_TSSI_ON_USE_EDGE_MASK 0x08000000                // CR_BAND_DGC_TSSI_ON_USE_EDGE[27]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DGC_TSSI_ON_USE_EDGE_SHFT 27
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEPARATE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEPARATE_MASK 0x04000000                // CR_BAND_RXFE_EN_SEPARATE[26]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEPARATE_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEL_MASK 0x02000000                // CR_BAND_RXFE_EN_SEL[25]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RXFE_EN_SEL_SHFT 25
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_GAIN_FORCE_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_GAIN_FORCE_EN_MASK 0x01000000                // CR_BAND_RFDGC_GAIN_FORCE_EN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_GAIN_FORCE_EN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_DEFAULT_GAIN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_DEFAULT_GAIN_MASK 0x003F0000                // CR_BAND_RFDGC_DEFAULT_GAIN[21..16]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_RFDGC_DEFAULT_GAIN_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC4_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC4_EN_MASK 0x00004000                // CR_BAND_TSSI_CIC4_EN[14]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC4_EN_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC5_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC5_EN_MASK 0x00002000                // CR_BAND_TSSI_CIC5_EN[13]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_CIC5_EN_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_MAN_MASK 0x00001000                // CR_BAND_TSSI_MAN[12]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_TSSI_MAN_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_SHARED_DBG_RX_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_SHARED_DBG_RX_SEL_MASK 0x00000200                // CR_BAND_SHARED_DBG_RX_SEL[9]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_SHARED_DBG_RX_SEL_SHFT 9
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_RD_RST_DISABLE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_RD_RST_DISABLE_MASK 0x00000100                // CR_BAND_AFIFO_RD_RST_DISABLE[8]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_RD_RST_DISABLE_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_WR_RST_DISABLE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_WR_RST_DISABLE_MASK 0x00000080                // CR_BAND_AFIFO_WR_RST_DISABLE[7]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_AFIFO_WR_RST_DISABLE_SHFT 7
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DLPF_RST_DISABLE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DLPF_RST_DISABLE_MASK 0x00000040                // CR_BAND_DLPF_RST_DISABLE[6]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_DLPF_RST_DISABLE_SHFT 6
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_IQC_RST_DISABLE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_IQC_RST_DISABLE_MASK 0x00000020                // CR_BAND_IQC_RST_DISABLE[5]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_IQC_RST_DISABLE_SHFT 5
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_VRCF_RST_DISABLE_ADDR BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_VRCF_RST_DISABLE_MASK 0x00000008                // CR_BAND_VRCF_RST_DISABLE[3]
#define BN0_PHYDFE_CTRL_CR_BAND_WF_RXFE_02_CR_BAND_VRCF_RST_DISABLE_SHFT 3

/* =====================================================================================

  ---CR_BAND_RXFE_H_VALGH_RATE_FLT (0x83080000 + 0xF070)---

    CR_BAND_NYF_TAP_SEL[1..0]    - (RW) NYF 12 tap or 30 tap manual select,  0 is 30
    RESERVED2[3..2]              - (RO) Reserved bits
    CR_BAND_MANUAL_BB_RATE_MODE[6..4] - (RW) manual rate mode of FIFO out, 0 is 1x, 1 is 2x, 2 is 4x
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_MANUAL_NYF_RATE[11..8] - (RW) manual rate mode of NYF out, 0 is 1x, 1 is 2x, 2 is 4x
    CR_BAND_CIC5_MANUAL_ON[13..12] - (RW) CIC5 filter manual mode
    CR_BAND_CIC4_MANUAL_ON[15..14] - (RW) CIC4 filter manual mode
    RESERVED16[18..16]           - (RO) Reserved bits
    CR_BAND_BYPASS_FDIQ_COMP[19] - (RW) bypass RXFDIQ compensation
    RESERVED20[27..20]           - (RO) Reserved bits
    CR_BAND_WB_INTF_EN[30..28]   - (RW) WB input selection enable when recieves interference
                                     28 : agv_amplitude en
                                     29 : AACI en
                                     30 : ACI en
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_WB_INTF_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_WB_INTF_EN_MASK 0x70000000                // CR_BAND_WB_INTF_EN[30..28]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_WB_INTF_EN_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_BYPASS_FDIQ_COMP_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_BYPASS_FDIQ_COMP_MASK 0x00080000                // CR_BAND_BYPASS_FDIQ_COMP[19]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_BYPASS_FDIQ_COMP_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC4_MANUAL_ON_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC4_MANUAL_ON_MASK 0x0000C000                // CR_BAND_CIC4_MANUAL_ON[15..14]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC4_MANUAL_ON_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC5_MANUAL_ON_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC5_MANUAL_ON_MASK 0x00003000                // CR_BAND_CIC5_MANUAL_ON[13..12]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_CIC5_MANUAL_ON_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_NYF_RATE_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_NYF_RATE_MASK 0x00000F00                // CR_BAND_MANUAL_NYF_RATE[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_NYF_RATE_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_BB_RATE_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_BB_RATE_MODE_MASK 0x00000070                // CR_BAND_MANUAL_BB_RATE_MODE[6..4]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_MANUAL_BB_RATE_MODE_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_NYF_TAP_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_NYF_TAP_SEL_MASK 0x00000003                // CR_BAND_NYF_TAP_SEL[1..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_H_VALGH_RATE_FLT_CR_BAND_NYF_TAP_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_AIC_CTRL_0 (0x83080000 + 0xF074)---

    CR_BAND_RXFE_AIC_COEF_I_00[6..0] - (RW) [CSD] AIC coef_00 I
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_Q_00[14..8] - (RW) [CSD] AIC coef_00 Q
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_I_01[22..16] - (RW) [CSD] AIC coef_01 I
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_Q_01[30..24] - (RW) [CSD] AIC coef_01 Q
    CR_BAND_RXFE_AIC_EN[31]      - (RW) [CSD] AIC enable

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_EN_MASK 0x80000000                // CR_BAND_RXFE_AIC_EN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_EN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_01_MASK 0x7F000000                // CR_BAND_RXFE_AIC_COEF_Q_01[30..24]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_01_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_01_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_01_MASK 0x007F0000                // CR_BAND_RXFE_AIC_COEF_I_01[22..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_01_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_00_MASK 0x00007F00                // CR_BAND_RXFE_AIC_COEF_Q_00[14..8]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_Q_00_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_00_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_00_MASK 0x0000007F                // CR_BAND_RXFE_AIC_COEF_I_00[6..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_0_CR_BAND_RXFE_AIC_COEF_I_00_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_AIC_CTRL_1 (0x83080000 + 0xF078)---

    CR_BAND_RXFE_AIC_COEF_I_10[6..0] - (RW) [CSD] AIC coef_10 I
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_Q_10[14..8] - (RW) [CSD] AIC coef_10 Q
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_I_11[22..16] - (RW) [CSD] AIC coef_11 I
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND_RXFE_AIC_COEF_Q_11[30..24] - (RW) [CSD] AIC coef_11 Q
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_11_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_11_MASK 0x7F000000                // CR_BAND_RXFE_AIC_COEF_Q_11[30..24]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_11_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_11_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_11_MASK 0x007F0000                // CR_BAND_RXFE_AIC_COEF_I_11[22..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_11_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_10_MASK 0x00007F00                // CR_BAND_RXFE_AIC_COEF_Q_10[14..8]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_Q_10_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_10_MASK 0x0000007F                // CR_BAND_RXFE_AIC_COEF_I_10[6..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_1_CR_BAND_RXFE_AIC_COEF_I_10_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_AIC_CTRL_2 (0x83080000 + 0xF07C)---

    CR_BAND_RXFE_AIC_RXSEL[3..0] - (RW) [DE] AIC rx manual select
    RESERVED4[6..4]              - (RO) Reserved bits
    CR_BAND_RXFE_AIC_RXSEL_MAN[7] - (RW) [DE] AIC rx manual select enable
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_MAN_MASK 0x00000080                // CR_BAND_RXFE_AIC_RXSEL_MAN[7]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_MAN_SHFT 7
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_MASK 0x0000000F                // CR_BAND_RXFE_AIC_RXSEL[3..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_AIC_CTRL_2_CR_BAND_RXFE_AIC_RXSEL_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADCIN_SEL (0x83080000 + 0xF080)---

    CR_BAND_RXADC_S2P_JM5[1..0]  - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_JM10[3..2] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_BW20[5..4] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_BW40[7..6] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_BW80[9..8] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_BW160[11..10] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_TSSI[13..12] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_S2P_MAN_VAL[15..14] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_NYF_JM5[16]    - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_JM10[17]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_BW20[18]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_BW40[19]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_BW80[20]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_BW160[21]  - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_TSSI[22]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_NYF_MAN_VAL[23] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_S2P_BW80_AA[25..24] - (RW) Serial to Parallel RXADC clock sel - 0 = no div, 1 = div2, 2 = dvi4 , 3 = div8
    CR_BAND_RXADC_NYF_BW80_AA[26] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    RESERVED27[29..27]           - (RO) Reserved bits
    CR_BAND_RXADC_S2P_MAN_EN[30] - (RW) Serial to Parallel RXADC clock sel manual mode
    CR_BAND_RXADC_NYF_MAN_EN[31] - (RW) NYF RXADC clock sel manual mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_EN_MASK 0x80000000                // CR_BAND_RXADC_NYF_MAN_EN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_EN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_EN_MASK 0x40000000                // CR_BAND_RXADC_S2P_MAN_EN[30]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_EN_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_AA_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_AA_MASK 0x04000000                // CR_BAND_RXADC_NYF_BW80_AA[26]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_AA_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_AA_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_AA_MASK 0x03000000                // CR_BAND_RXADC_S2P_BW80_AA[25..24]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_AA_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_VAL_MASK 0x00800000                // CR_BAND_RXADC_NYF_MAN_VAL[23]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_MAN_VAL_SHFT 23
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_TSSI_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_TSSI_MASK 0x00400000                // CR_BAND_RXADC_NYF_TSSI[22]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_TSSI_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW160_MASK 0x00200000                // CR_BAND_RXADC_NYF_BW160[21]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW160_SHFT 21
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_MASK 0x00100000                // CR_BAND_RXADC_NYF_BW80[20]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW80_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW40_MASK 0x00080000                // CR_BAND_RXADC_NYF_BW40[19]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW40_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW20_MASK 0x00040000                // CR_BAND_RXADC_NYF_BW20[18]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_BW20_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM10_MASK 0x00020000                // CR_BAND_RXADC_NYF_JM10[17]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM10_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM5_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM5_MASK 0x00010000                // CR_BAND_RXADC_NYF_JM5[16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_NYF_JM5_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_VAL_MASK 0x0000C000                // CR_BAND_RXADC_S2P_MAN_VAL[15..14]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_MAN_VAL_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_TSSI_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_TSSI_MASK 0x00003000                // CR_BAND_RXADC_S2P_TSSI[13..12]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_TSSI_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW160_MASK 0x00000C00                // CR_BAND_RXADC_S2P_BW160[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW160_SHFT 10
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_MASK 0x00000300                // CR_BAND_RXADC_S2P_BW80[9..8]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW80_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW40_MASK 0x000000C0                // CR_BAND_RXADC_S2P_BW40[7..6]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW40_SHFT 6
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW20_MASK 0x00000030                // CR_BAND_RXADC_S2P_BW20[5..4]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_BW20_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM10_MASK 0x0000000C                // CR_BAND_RXADC_S2P_JM10[3..2]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM10_SHFT 2
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM5_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM5_MASK 0x00000003                // CR_BAND_RXADC_S2P_JM5[1..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_CR_BAND_RXADC_S2P_JM5_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADCIN_SEL_1 (0x83080000 + 0xF084)---

    CR_BAND_RXADC_DS2_JM5[0]     - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_JM10[1]    - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_BW20[2]    - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_BW40[3]    - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_BW80[4]    - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_BW160[5]   - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_TSSI[6]    - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_DS2_MAN_VAL[7] - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_2DCOC_JM5[8]   - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_JM10[9]  - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_BW20[10] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_BW40[11] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_BW80[12] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_BW160[13] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_TSSI[14] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_2DCOC_MAN_VAL[15] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    CR_BAND_RXADC_DS2_BW80_AA[16] - (RW) down sample 2 before cic4 filter enable
    CR_BAND_RXADC_2DCOC_BW80_AA[17] - (RW) NYF RXADC clock sel - 0 = div2 , 1 = div3
    RESERVED18[23..18]           - (RO) Reserved bits
    CR_BAND_RXADC_DS2_MAN_EN[24] - (RW) Serial to Parallel RXADC clock sel manual mode
    CR_BAND_RXADC_2DCOC_MAN_EN[25] - (RW) NYF RXADC clock sel manual mode
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_EN_MASK 0x02000000                // CR_BAND_RXADC_2DCOC_MAN_EN[25]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_EN_SHFT 25
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_EN_MASK 0x01000000                // CR_BAND_RXADC_DS2_MAN_EN[24]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_EN_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_AA_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_AA_MASK 0x00020000                // CR_BAND_RXADC_2DCOC_BW80_AA[17]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_AA_SHFT 17
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_AA_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_AA_MASK 0x00010000                // CR_BAND_RXADC_DS2_BW80_AA[16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_AA_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_VAL_MASK 0x00008000                // CR_BAND_RXADC_2DCOC_MAN_VAL[15]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_MAN_VAL_SHFT 15
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_TSSI_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_TSSI_MASK 0x00004000                // CR_BAND_RXADC_2DCOC_TSSI[14]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_TSSI_SHFT 14
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW160_MASK 0x00002000                // CR_BAND_RXADC_2DCOC_BW160[13]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW160_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_MASK 0x00001000                // CR_BAND_RXADC_2DCOC_BW80[12]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW80_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW40_MASK 0x00000800                // CR_BAND_RXADC_2DCOC_BW40[11]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW40_SHFT 11
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW20_MASK 0x00000400                // CR_BAND_RXADC_2DCOC_BW20[10]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_BW20_SHFT 10
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM10_MASK 0x00000200                // CR_BAND_RXADC_2DCOC_JM10[9]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM10_SHFT 9
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM5_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM5_MASK 0x00000100                // CR_BAND_RXADC_2DCOC_JM5[8]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_2DCOC_JM5_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_VAL_MASK 0x00000080                // CR_BAND_RXADC_DS2_MAN_VAL[7]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_MAN_VAL_SHFT 7
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_TSSI_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_TSSI_MASK 0x00000040                // CR_BAND_RXADC_DS2_TSSI[6]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_TSSI_SHFT 6
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW160_MASK 0x00000020                // CR_BAND_RXADC_DS2_BW160[5]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW160_SHFT 5
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_MASK 0x00000010                // CR_BAND_RXADC_DS2_BW80[4]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW80_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW40_MASK 0x00000008                // CR_BAND_RXADC_DS2_BW40[3]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW40_SHFT 3
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW20_MASK 0x00000004                // CR_BAND_RXADC_DS2_BW20[2]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_BW20_SHFT 2
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM10_MASK 0x00000002                // CR_BAND_RXADC_DS2_JM10[1]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM10_SHFT 1
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM5_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM5_MASK 0x00000001                // CR_BAND_RXADC_DS2_JM5[0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADCIN_SEL_1_CR_BAND_RXADC_DS2_JM5_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_CKSEL_0 (0x83080000 + 0xF090)---

    CR_BAND_RXADC_CKSEL_TSSI[14..0] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXADC_CKSEL_MAN_VAL[30..16] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    CR_BAND_RXADC_CKSEL_MAN_EN[31] - (RW) ADC clcok divide manual mode

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_EN_MASK 0x80000000                // CR_BAND_RXADC_CKSEL_MAN_EN[31]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_EN_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_VAL_MASK 0x7FFF0000                // CR_BAND_RXADC_CKSEL_MAN_VAL[30..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_MAN_VAL_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_TSSI_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_TSSI_MASK 0x00007FFF                // CR_BAND_RXADC_CKSEL_TSSI[14..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_0_CR_BAND_RXADC_CKSEL_TSSI_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_CKSEL_1 (0x83080000 + 0xF094)---

    CR_BAND_RXADC_CKSEL_BW80[14..0] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXADC_CKSEL_BW160[30..16] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW160_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW160_MASK 0x7FFF0000                // CR_BAND_RXADC_CKSEL_BW160[30..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW160_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW80_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW80_MASK 0x00007FFF                // CR_BAND_RXADC_CKSEL_BW80[14..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_1_CR_BAND_RXADC_CKSEL_BW80_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_CKSEL_2 (0x83080000 + 0xF098)---

    CR_BAND_RXADC_CKSEL_BW20[14..0] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXADC_CKSEL_BW40[30..16] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW40_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW40_MASK 0x7FFF0000                // CR_BAND_RXADC_CKSEL_BW40[30..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW40_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW20_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW20_MASK 0x00007FFF                // CR_BAND_RXADC_CKSEL_BW20[14..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_2_CR_BAND_RXADC_CKSEL_BW20_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_CKSEL_3 (0x83080000 + 0xF09C)---

    CR_BAND_RXADC_CKSEL_JM5[14..0] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_RXADC_CKSEL_JM10[30..16] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM10_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM10_MASK 0x7FFF0000                // CR_BAND_RXADC_CKSEL_JM10[30..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM10_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM5_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM5_MASK 0x00007FFF                // CR_BAND_RXADC_CKSEL_JM5[14..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_3_CR_BAND_RXADC_CKSEL_JM5_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_ADC_CKSEL_4 (0x83080000 + 0xF0A0)---

    CR_BAND_RXADC_CKSEL_BW80_AA[14..0] - (RW) ADC clcok divide selector : {nyf[3:0], s2p[2:0], cic5[1:0], cic4[1:0], dcoc[1:0], adc_in[1:0] }
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_4_CR_BAND_RXADC_CKSEL_BW80_AA_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_4_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_4_CR_BAND_RXADC_CKSEL_BW80_AA_MASK 0x00007FFF                // CR_BAND_RXADC_CKSEL_BW80_AA[14..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_ADC_CKSEL_4_CR_BAND_RXADC_CKSEL_BW80_AA_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_CTRL_00 (0x83080000 + 0xF0A4)---

    RESERVED0[29..0]             - (RO) Reserved bits
    CR_BAND_BYPASS_RU_NOTCH[30]  - (RW)  xxx 
    CR_BAND_RXFE_ADC_AA_MODE[31] - (RW)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_RXFE_ADC_AA_MODE_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_RXFE_ADC_AA_MODE_MASK 0x80000000                // CR_BAND_RXFE_ADC_AA_MODE[31]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_RXFE_ADC_AA_MODE_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_BYPASS_RU_NOTCH_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_BYPASS_RU_NOTCH_MASK 0x40000000                // CR_BAND_BYPASS_RU_NOTCH[30]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_CTRL_00_CR_BAND_BYPASS_RU_NOTCH_SHFT 30

/* =====================================================================================

  ---RO_BAND_WB_RSSI_AMP_AVG (0x83080000 + 0xF0B0)---

    RO_BAND_WB_RSSI_AMP_AVG[31..0] - (RO) WB RSSI value
                                     [24:16] RX1 value, 
                                     [8:0] RX0 value

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_WB_RSSI_AMP_AVG_RO_BAND_WB_RSSI_AMP_AVG_ADDR BN0_PHYDFE_CTRL_RO_BAND_WB_RSSI_AMP_AVG_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_WB_RSSI_AMP_AVG_RO_BAND_WB_RSSI_AMP_AVG_MASK 0xFFFFFFFF                // RO_BAND_WB_RSSI_AMP_AVG[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_WB_RSSI_AMP_AVG_RO_BAND_WB_RSSI_AMP_AVG_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_CTL_00_RD (0x83080000 + 0xF0B4)---

    RO_BAND_RXFE_DBG_CTL_00_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_CTL_00_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_CTL_00_RD_RO_BAND_RXFE_DBG_CTL_00_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_CTL_00_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_CTL_00_RD_RO_BAND_RXFE_DBG_CTL_00_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_CTL_00_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_CTL_00_RD_RO_BAND_RXFE_DBG_CTL_00_RD_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_AFIFO_RD (0x83080000 + 0xF0B8)---

    RO_BAND_RXFE_DBG_AFIFO_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_AFIFO_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_AFIFO_RD_RO_BAND_RXFE_DBG_AFIFO_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_AFIFO_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_AFIFO_RD_RO_BAND_RXFE_DBG_AFIFO_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_AFIFO_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_AFIFO_RD_RO_BAND_RXFE_DBG_AFIFO_RD_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_VRCF_RD_RX0 (0x83080000 + 0xF0BC)---

    RO_BAND_RXFE_DBG_VRCF_RD_RX0[31..0] - (RO) RO_BAND0_RXFE_DBG_VRCF_RD_RX0

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX0_RO_BAND_RXFE_DBG_VRCF_RD_RX0_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX0_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX0_RO_BAND_RXFE_DBG_VRCF_RD_RX0_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_VRCF_RD_RX0[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX0_RO_BAND_RXFE_DBG_VRCF_RD_RX0_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_VRCF_RD_RX1 (0x83080000 + 0xF0C0)---

    RO_BAND_RXFE_DBG_VRCF_RD_RX1[31..0] - (RO) RO_BAND0_RXFE_DBG_VRCF_RD_RX1

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX1_RO_BAND_RXFE_DBG_VRCF_RD_RX1_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX1_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX1_RO_BAND_RXFE_DBG_VRCF_RD_RX1_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_VRCF_RD_RX1[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_VRCF_RD_RX1_RO_BAND_RXFE_DBG_VRCF_RD_RX1_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_NOTCH_00_RD (0x83080000 + 0xF0C4)---

    RO_BAND_RXFE_DBG_NOTCH_00_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_NOTCH_00_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_00_RD_RO_BAND_RXFE_DBG_NOTCH_00_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_00_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_00_RD_RO_BAND_RXFE_DBG_NOTCH_00_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_NOTCH_00_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_00_RD_RO_BAND_RXFE_DBG_NOTCH_00_RD_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_NOTCH_01_RD (0x83080000 + 0xF0C8)---

    RO_BAND_RXFE_DBG_NOTCH_01_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_NOTCH_01_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_01_RD_RO_BAND_RXFE_DBG_NOTCH_01_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_01_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_01_RD_RO_BAND_RXFE_DBG_NOTCH_01_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_NOTCH_01_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_01_RD_RO_BAND_RXFE_DBG_NOTCH_01_RD_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_NOTCH_02_RD (0x83080000 + 0xF0CC)---

    RO_BAND_RXFE_DBG_NOTCH_02_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_NOTCH_02_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_02_RD_RO_BAND_RXFE_DBG_NOTCH_02_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_02_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_02_RD_RO_BAND_RXFE_DBG_NOTCH_02_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_NOTCH_02_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_02_RD_RO_BAND_RXFE_DBG_NOTCH_02_RD_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_NOTCH_03_RD (0x83080000 + 0xF0D0)---

    RO_BAND_RXFE_DBG_NOTCH_03_RD[31..0] - (RO) RO_BAND0_RXFE_DBG_NOTCH_02_RD

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_03_RD_RO_BAND_RXFE_DBG_NOTCH_03_RD_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_03_RD_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_03_RD_RO_BAND_RXFE_DBG_NOTCH_03_RD_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_NOTCH_03_RD[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_NOTCH_03_RD_RO_BAND_RXFE_DBG_NOTCH_03_RD_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_SFO_INTPO_1 (0x83080000 + 0xF100)---

    CR_BAND_RXFE_INTPO_CFOE_SYN[19..0] - (RW) [CSD] s-5,24, SW compensation synthesier FO
    CR_BAND_RXFE_INTPO_COMP_CFOE_TH[29..20] - (RW) [CSD] s-5,15,Threshold to take cfoe_pd into sfoe calculation
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_COMP_CFOE_TH_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_COMP_CFOE_TH_MASK 0x3FF00000                // CR_BAND_RXFE_INTPO_COMP_CFOE_TH[29..20]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_COMP_CFOE_TH_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_CFOE_SYN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_CFOE_SYN_MASK 0x000FFFFF                // CR_BAND_RXFE_INTPO_CFOE_SYN[19..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_1_CR_BAND_RXFE_INTPO_CFOE_SYN_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_SFO_INTPO_2 (0x83080000 + 0xF104)---

    CR_BAND_RXFE_INTPO_COMP_ENB_TH[9..0] - (RW) [CSD] u-11,21,unit: ppm Threshold for trigger RXINTPO
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_BAND_RXFE_INTPO_COMP_OUT_BUFFER_DEPTH[15..12] - (RW) [CSD] SFO IO buffer depth, max_length*T_fs*ppm
    CR_BAND_RXFE_INTPO_G_VALUE[27..16] - (RW) [CSD] s-6,17, 20/Fc_MHz
    CR_BAND_RXFE_INTPO_LOOP_GAIN[31..28] - (RW) [CSD] u1,3, Loop gain, value/8

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_LOOP_GAIN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_LOOP_GAIN_MASK 0xF0000000                // CR_BAND_RXFE_INTPO_LOOP_GAIN[31..28]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_LOOP_GAIN_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_G_VALUE_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_G_VALUE_MASK 0x0FFF0000                // CR_BAND_RXFE_INTPO_G_VALUE[27..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_G_VALUE_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_OUT_BUFFER_DEPTH_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_OUT_BUFFER_DEPTH_MASK 0x0000F000                // CR_BAND_RXFE_INTPO_COMP_OUT_BUFFER_DEPTH[15..12]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_OUT_BUFFER_DEPTH_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_ENB_TH_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_ENB_TH_MASK 0x000003FF                // CR_BAND_RXFE_INTPO_COMP_ENB_TH[9..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_2_CR_BAND_RXFE_INTPO_COMP_ENB_TH_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_SFO_INTPO_3 (0x83080000 + 0xF108)---

    CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL[10..0] - (RW) [CSD] Active when CR_BAND_RXFE_INTPO_MANUAL enabled
                                     s-5.21,manual d_tau value for RXINTPO
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND_RXFE_INTPO_MANUAL_ENB[12] - (RW) [CSD] Active when CR_BAND_RXFE_INTPO_MANUAL enabled
                                     0: DISABLE 
                                     1: ENABLE
    CR_BAND_RXFE_INTPO_MANUAL[13] - (RW) [CSD]  Manual mode
                                     0: DISABLE 
                                     1: ENABLE
                                     If ENABLE, delta_mu value is forced by CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL
                                     RX_Itpo_enb is decided by CR_BAND_RXFE_INTPO_MANUAL_ENB
    RESERVED14[14]               - (RO) Reserved bits
    CR_BAND_RXFE_INTPO_SFOE_POLARITY[15] - (RW) [CSD]  SFOE polarity check
                                     0: Adjust Polarity
                                     1: Keep Polarity
    CR_BAND_RXFE_INTPO_MANUAL_SFOE_OFT_INTPO[31..16] - (RW) [CSD] Active when CR_BAND_RXFE_INTPO_MANUAL enabled
                                     Manual sfo_offset_comp_intPO  value for RXINTPO, to TFT

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_SFOE_OFT_INTPO_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_SFOE_OFT_INTPO_MASK 0xFFFF0000                // CR_BAND_RXFE_INTPO_MANUAL_SFOE_OFT_INTPO[31..16]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_SFOE_OFT_INTPO_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_SFOE_POLARITY_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_SFOE_POLARITY_MASK 0x00008000                // CR_BAND_RXFE_INTPO_SFOE_POLARITY[15]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_SFOE_POLARITY_SHFT 15
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_MASK 0x00002000                // CR_BAND_RXFE_INTPO_MANUAL[13]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_ENB_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_ENB_MASK 0x00001000                // CR_BAND_RXFE_INTPO_MANUAL_ENB[12]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_ENB_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL_MASK 0x000007FF                // CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL[10..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_3_CR_BAND_RXFE_INTPO_MANUAL_DTAU_VAL_SHFT 0

/* =====================================================================================

  ---CR_BAND_RXFE_SFO_INTPO_4 (0x83080000 + 0xF10C)---

    CR_BAND_RXFE_INTPO_SFOE_SYN[15..0] - (RW) [CSD] s-11,26, SW compensation SFO (DISABLED)
    RESERVED16[17..16]           - (RO) Reserved bits
    CR_BAND_RXFE_INTPO_SYN_ENB[18] - (RW) [CSD] Ctrl signal for using Synthesizer method
    CR_BAND_RXFE_INTPO_SYN_UPDATE_VLD[19] - (RW) [CSD] SW table valid signal for using Synthesizer method
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_UPDATE_VLD_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_UPDATE_VLD_MASK 0x00080000                // CR_BAND_RXFE_INTPO_SYN_UPDATE_VLD[19]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_UPDATE_VLD_SHFT 19
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_ENB_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_ENB_MASK 0x00040000                // CR_BAND_RXFE_INTPO_SYN_ENB[18]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SYN_ENB_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SFOE_SYN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SFOE_SYN_MASK 0x0000FFFF                // CR_BAND_RXFE_INTPO_SFOE_SYN[15..0]
#define BN0_PHYDFE_CTRL_CR_BAND_RXFE_SFO_INTPO_4_CR_BAND_RXFE_INTPO_SFOE_SYN_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_SFO_INTPO_00 (0x83080000 + 0xF120)---

    RO_BAND_RXFE_DBG_SFO_INTPO_00[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_00_RO_BAND_RXFE_DBG_SFO_INTPO_00_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_00_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_00_RO_BAND_RXFE_DBG_SFO_INTPO_00_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_SFO_INTPO_00[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_00_RO_BAND_RXFE_DBG_SFO_INTPO_00_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_SFO_INTPO_01 (0x83080000 + 0xF124)---

    RO_BAND_RXFE_DBG_SFO_INTPO_01[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_01_RO_BAND_RXFE_DBG_SFO_INTPO_01_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_01_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_01_RO_BAND_RXFE_DBG_SFO_INTPO_01_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_SFO_INTPO_01[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_01_RO_BAND_RXFE_DBG_SFO_INTPO_01_SHFT 0

/* =====================================================================================

  ---RO_BAND_RXFE_DBG_SFO_INTPO_02 (0x83080000 + 0xF128)---

    RO_BAND_RXFE_DBG_SFO_INTPO_02[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_02_RO_BAND_RXFE_DBG_SFO_INTPO_02_ADDR BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_02_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_02_RO_BAND_RXFE_DBG_SFO_INTPO_02_MASK 0xFFFFFFFF                // RO_BAND_RXFE_DBG_SFO_INTPO_02[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RXFE_DBG_SFO_INTPO_02_RO_BAND_RXFE_DBG_SFO_INTPO_02_SHFT 0

/* =====================================================================================

  ---CR_BAND_TXPTN_CTL_0 (0x83080000 + 0xFC00)---

    CR_BAND_TXPATN_MANU_IP[6..0] - (RW)  xxx 
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND_TXPATN_MANU_DS[14..8] - (RW)  xxx 
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND_TXPATN_MANU_BW[17..16] - (RW)  xxx 
    CR_BAND_TXPATN_MANU_TT[19..18] - (RW)  xxx 
    CR_BAND_TXPATN_MANU_OS[22..20] - (RW)  xxx 
    CR_BAND_TXPATN_MANU_3X[23]   - (RW)  xxx 
    CR_BAND_TXPATN_MANU_MS[24]   - (RW)  xxx 
    CR_BAND_TXPATN_MANU_TS[25]   - (RW)  xxx 
    CR_BAND_TXPATN_MANU_MP[26]   - (RW)  xxx 
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND_TXPATN_CAL_MODE_EN[28] - (RW)  xxx 
    CR_BAND_TXPATN_INIT_PHASE_EN[29] - (RW)  xxx 
    CR_BAND_TXPATN_EN_TONE[30]   - (RW)  xxx 
    CR_BAND_TXPATN_MANU[31]      - (RW)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MASK 0x80000000                // CR_BAND_TXPATN_MANU[31]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_EN_TONE_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_EN_TONE_MASK 0x40000000                // CR_BAND_TXPATN_EN_TONE[30]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_EN_TONE_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_INIT_PHASE_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_INIT_PHASE_EN_MASK 0x20000000                // CR_BAND_TXPATN_INIT_PHASE_EN[29]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_INIT_PHASE_EN_SHFT 29
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_CAL_MODE_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_CAL_MODE_EN_MASK 0x10000000                // CR_BAND_TXPATN_CAL_MODE_EN[28]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_CAL_MODE_EN_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MP_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MP_MASK 0x04000000                // CR_BAND_TXPATN_MANU_MP[26]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MP_SHFT 26
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TS_MASK 0x02000000                // CR_BAND_TXPATN_MANU_TS[25]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TS_SHFT 25
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MS_MASK 0x01000000                // CR_BAND_TXPATN_MANU_MS[24]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_MS_SHFT 24
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_3X_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_3X_MASK 0x00800000                // CR_BAND_TXPATN_MANU_3X[23]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_3X_SHFT 23
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_OS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_OS_MASK 0x00700000                // CR_BAND_TXPATN_MANU_OS[22..20]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_OS_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TT_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TT_MASK 0x000C0000                // CR_BAND_TXPATN_MANU_TT[19..18]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_TT_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_BW_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_BW_MASK 0x00030000                // CR_BAND_TXPATN_MANU_BW[17..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_BW_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_DS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_DS_MASK 0x00007F00                // CR_BAND_TXPATN_MANU_DS[14..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_DS_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_IP_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_IP_MASK 0x0000007F                // CR_BAND_TXPATN_MANU_IP[6..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_0_CR_BAND_TXPATN_MANU_IP_SHFT 0

/* =====================================================================================

  ---CR_BAND_TXPTN_CTL_1 (0x83080000 + 0xFC04)---

    CR_BAND_TXPATN_PN_VAR[7..0]  - (RW)  xxx 
    CR_BAND_TXPATN_PN_BYPASS[8]  - (RW)  xxx 
    CR_BAND_TXPATN_PN_RST[9]     - (RW)  xxx 
    CR_BAND_TXPATN_SOURCE_SEL[11..10] - (RW)  xxx 
    CR_BAND_TXPATN_TRIG_BY_AWG[12] - (RW)  xxx 
    CR_BAND_TXPATN_PN_GEN_RST_ROLLBACK[13] - (RW)  xxx 
    RESERVED14[17..14]           - (RO) Reserved bits
    CR_BAND_TXPATN_VLD_DLY[19..18] - (RW)  xxx 
    CR_BAND_TXPATN_BTR_DELAY[20] - (RW)  xxx 
    CR_BAND_TXPATN_DPD_SEL[21]   - (RW)  xxx 
    CR_BAND_TXPATN_FORCE_DC[22]  - (RW)  xxx 
    CR_BAND_TXPATN_FORCE_VALID[23] - (RW)  xxx 
    RESERVED24[26..24]           - (RO) Reserved bits
    CR_BAND_TXPATN_EN_WEIGHT[27] - (RW)  xxx 
    CR_BAND_TXPATN_EN_RAMP[28]   - (RW)  xxx 
    CR_BAND_TXPATN_EN_SYNC[29]   - (RW)  xxx 
    CR_BAND_TXPATN_EN_UP2X[30]   - (RW)  xxx 
    CR_BAND_TXPATN_EN_FIFO[31]   - (RW)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_FIFO_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_FIFO_MASK 0x80000000                // CR_BAND_TXPATN_EN_FIFO[31]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_FIFO_SHFT 31
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_UP2X_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_UP2X_MASK 0x40000000                // CR_BAND_TXPATN_EN_UP2X[30]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_UP2X_SHFT 30
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_SYNC_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_SYNC_MASK 0x20000000                // CR_BAND_TXPATN_EN_SYNC[29]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_SYNC_SHFT 29
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_RAMP_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_RAMP_MASK 0x10000000                // CR_BAND_TXPATN_EN_RAMP[28]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_RAMP_SHFT 28
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_WEIGHT_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_WEIGHT_MASK 0x08000000                // CR_BAND_TXPATN_EN_WEIGHT[27]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_EN_WEIGHT_SHFT 27
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_VALID_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_VALID_MASK 0x00800000                // CR_BAND_TXPATN_FORCE_VALID[23]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_VALID_SHFT 23
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_DC_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_DC_MASK 0x00400000                // CR_BAND_TXPATN_FORCE_DC[22]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_FORCE_DC_SHFT 22
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_DPD_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_DPD_SEL_MASK 0x00200000                // CR_BAND_TXPATN_DPD_SEL[21]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_DPD_SEL_SHFT 21
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_BTR_DELAY_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_BTR_DELAY_MASK 0x00100000                // CR_BAND_TXPATN_BTR_DELAY[20]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_BTR_DELAY_SHFT 20
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_VLD_DLY_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_VLD_DLY_MASK 0x000C0000                // CR_BAND_TXPATN_VLD_DLY[19..18]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_VLD_DLY_SHFT 18
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_GEN_RST_ROLLBACK_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_GEN_RST_ROLLBACK_MASK 0x00002000                // CR_BAND_TXPATN_PN_GEN_RST_ROLLBACK[13]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_GEN_RST_ROLLBACK_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_TRIG_BY_AWG_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_TRIG_BY_AWG_MASK 0x00001000                // CR_BAND_TXPATN_TRIG_BY_AWG[12]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_TRIG_BY_AWG_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_SOURCE_SEL_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_SOURCE_SEL_MASK 0x00000C00                // CR_BAND_TXPATN_SOURCE_SEL[11..10]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_SOURCE_SEL_SHFT 10
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_RST_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_RST_MASK 0x00000200                // CR_BAND_TXPATN_PN_RST[9]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_RST_SHFT 9
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_BYPASS_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_BYPASS_MASK 0x00000100                // CR_BAND_TXPATN_PN_BYPASS[8]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_BYPASS_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_VAR_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_VAR_MASK 0x000000FF                // CR_BAND_TXPATN_PN_VAR[7..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_1_CR_BAND_TXPATN_PN_VAR_SHFT 0

/* =====================================================================================

  ---CR_BAND_TXPTN_CTL_2 (0x83080000 + 0xFC08)---

    CR_BAND_TXPATN_DC_I[11..0]   - (RW)  xxx 
    RESERVED12[15..12]           - (RO) Reserved bits
    CR_BAND_TXPATN_DC_Q[27..16]  - (RW)  xxx 
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_Q_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_Q_MASK 0x0FFF0000                // CR_BAND_TXPATN_DC_Q[27..16]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_Q_SHFT 16
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_I_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_I_MASK 0x00000FFF                // CR_BAND_TXPATN_DC_I[11..0]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_2_CR_BAND_TXPATN_DC_I_SHFT 0

/* =====================================================================================

  ---CR_BAND_TXPTN_CTL_3 (0x83080000 + 0xFC0C)---

    CR_BAND_RFINTF_TX_CAL_RST[0] - (RW)  xxx 
    RESERVED1[3..1]              - (RO) Reserved bits
    CR_BAND_RFINTF_TXPTN_IND_MAN[5..4] - (RW)  xxx 
    RESERVED6[7..6]              - (RO) Reserved bits
    CR_BAND_RFINTF_TXCBW_IND_MAN[11..8] - (RW)  xxx 
    CR_BAND_RFINTF_TXPTN_IND_MAN_EN[12] - (RW)  xxx 
    CR_BAND_RFINTF_TXCBW_IND_MAN_EN[13] - (RW)  xxx 
    RESERVED14[31..14]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_EN_MASK 0x00002000                // CR_BAND_RFINTF_TXCBW_IND_MAN_EN[13]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_EN_SHFT 13
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_EN_MASK 0x00001000                // CR_BAND_RFINTF_TXPTN_IND_MAN_EN[12]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_EN_SHFT 12
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_MASK 0x00000F00                // CR_BAND_RFINTF_TXCBW_IND_MAN[11..8]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXCBW_IND_MAN_SHFT 8
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_MASK 0x00000030                // CR_BAND_RFINTF_TXPTN_IND_MAN[5..4]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TXPTN_IND_MAN_SHFT 4
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TX_CAL_RST_ADDR BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TX_CAL_RST_MASK 0x00000001                // CR_BAND_RFINTF_TX_CAL_RST[0]
#define BN0_PHYDFE_CTRL_CR_BAND_TXPTN_CTL_3_CR_BAND_RFINTF_TX_CAL_RST_SHFT 0

/* =====================================================================================

  ---CR_BAND_RFINTF_CTRL_0 (0x83080000 + 0xFC20)---

    CR_BAND_RFINTF_CAL_EN[0]     - (RW)  xxx 
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_CR_BAND_RFINTF_CTRL_0_CR_BAND_RFINTF_CAL_EN_ADDR BN0_PHYDFE_CTRL_CR_BAND_RFINTF_CTRL_0_ADDR
#define BN0_PHYDFE_CTRL_CR_BAND_RFINTF_CTRL_0_CR_BAND_RFINTF_CAL_EN_MASK 0x00000001                // CR_BAND_RFINTF_CAL_EN[0]
#define BN0_PHYDFE_CTRL_CR_BAND_RFINTF_CTRL_0_CR_BAND_RFINTF_CAL_EN_SHFT 0

/* =====================================================================================

  ---RO_BAND_RFINTF_FLAG_00 (0x83080000 + 0xFDE0)---

    RO_BAND_RFINTF_FLAG_00[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_RFINTF_FLAG_00_RO_BAND_RFINTF_FLAG_00_ADDR BN0_PHYDFE_CTRL_RO_BAND_RFINTF_FLAG_00_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_RFINTF_FLAG_00_RO_BAND_RFINTF_FLAG_00_MASK 0xFFFFFFFF                // RO_BAND_RFINTF_FLAG_00[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_RFINTF_FLAG_00_RO_BAND_RFINTF_FLAG_00_SHFT 0

/* =====================================================================================

  ---RO_BAND_TXPTN_DBG_0 (0x83080000 + 0xFDE4)---

    RO_BAND_TXPATN_STAT_00[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_0_RO_BAND_TXPATN_STAT_00_ADDR BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_0_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_0_RO_BAND_TXPATN_STAT_00_MASK 0xFFFFFFFF                // RO_BAND_TXPATN_STAT_00[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_0_RO_BAND_TXPATN_STAT_00_SHFT 0

/* =====================================================================================

  ---RO_BAND_TXPTN_DBG_1 (0x83080000 + 0xFDE8)---

    RO_BAND_TXPATN_STAT_01[31..0] - (RO)  xxx 

 =====================================================================================*/
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_1_RO_BAND_TXPATN_STAT_01_ADDR BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_1_ADDR
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_1_RO_BAND_TXPATN_STAT_01_MASK 0xFFFFFFFF                // RO_BAND_TXPATN_STAT_01[31..0]
#define BN0_PHYDFE_CTRL_RO_BAND_TXPTN_DBG_1_RO_BAND_TXPATN_STAT_01_SHFT 0

#ifdef __cplusplus
}
#endif

#endif // __BN0_PHYDFE_CTRL_REGS_H__
